A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Barth, J.; Plass, D.; Nelson, Erik; Hwang, C.; Fredeman, Gregory; Sperling, Michael; Mathews, Abraham; Kirihata, T.; Reohr, W.; Nair, Kavita; Caon, Nianzheng

doi:10.1109/jssc.2010.2084470

Cited by 45 publications

(22 citation statements)

References 12 publications

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“…Existing tools also do not provide the capability to model DWM and MLC, etc. As an increasing number of industrial designs utilizes 3D stacking [4,5], research on 3D stacking has become very important. However, existing 3D modeling tools such as CACTI-3DD [6] and 3DCacti [14] do not model NVMs.…”

Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%

“…To enable modeling of eDRAM, we separate the peripheral and device logic to simulate multiple types of technologies. eDRAM requires refresh for maintaining data integrity and typical retention periods range from 40 µs to 100 µs [4,5] for temperature in the range of 380 K. We implemented a refresh model based on Kirihata et al [47], in which all subarrays are refreshed in parallel, row-by-row. The benefit of this approach is that the refresh operations do not significantly reduce the availability of banks to service requests.…”

Section: Edram Modelmentioning

confidence: 99%

“…To validate against it, we use the 2-Mb macro layout with a total of eight subarrays and, thus, use the organization of a 1024 × 2048 bank layout. Klim et al [21] and Barth et al [4] present 45-nm 2D eDRAM designs. We validate against them using a subarray layout of 256 × 1024 as used by them.…”

Section: D and 3d Edram Validationmentioning

confidence: 99%

“…For example, eDRAM, STT-RAM, ReRAM, PCM, DWM, SOT-RAM and (NAND) Flash memory have received significant attention in recent years [3] (unless otherwise mentioned, in this paper, Flash refers to NAND Flash). Similarly, 3D integration technology has been explored for achieving higher bandwidth, higher flexibility in routing signals, power, clock and ability to integrate diverse memory technologies for designing hybrid memory designs [4,5]. Finally, since NVMs have a large resistance margin between set and reset states, MLC designs have been studied, which store multiple (e.g., two) bits in each cell to achieve higher density than the SLC designs.…”

Section: Introductionmentioning

confidence: 99%

“…Table 2 summarizes the capabilities of DESTINY and compares them with those of CACTI and NVSim. We have compared the results obtained from DESTINY against several commercial and research prototypes [4,5,11,[15][16][17][18][19][20][21][22][23][24][25][26] to validate the newly-added memories, MLC and 3D models in DESTINY (Section 5). The modeling error has been observed to be less than 10% for most cases and less than 25% for all cases.…”

Section: Introductionmentioning

confidence: 99%

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DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal

Wang

Vetter

2017

JLPEA

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Abstract:To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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Section: A Comparison Of Modeling Toolsmentioning

confidence: 99%