A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

Nii, H.; Sanuki, T.; Okayama, Y.; Ota, Kosuke; Iwamoto, Toshiyuki; Fujimaki, T.; Kimura, Taiki; Watanabe, Rikiya; Komoda, T.; Eiho, A.; Aikawa, Kyota; Yamaguchi, Hideyo; Morimoto, R.; Ohshima, Kazuaki; Yokoyama, T.; Matsumoto, Takeru; Hachimine, K.; Sogo, Y.; Shino, S.; Kanai, Shuichiro; Yamazaki, Taku; Takahashi, Shinichi; Maeda, H.; Iwata, T.; Ohno, Katsutoshi; Takegawa, Y.; Oishi, A.; Togo, M.; Fukasaku, K.; Takasu, Y.; Yamasaki, H.; Inokuma, H.; Matsuo, K.; Sato, Tsutomu; Nakazawa, M.; Katagiri, Takeshi; Nakazawa, K.; Shinyama, T.; Tetsuka, T.; Fujita, S.; Kagawa, Y.; Nagaoka, K.; Muramatsu, S.; Iwasa, S.; Motomizu, Shoji; Yoshida, Kenji; Sunouchi, K.; Iwai, M.; Saito, Masao; Ikeda, Masayuki; Enomoto, Y.; Naruse, H.; Imai, Ko; Yamada, Shigeru; Nishida, Naoki; Kuwata, T.; Matsuoka, F.

doi:10.1109/iedm.2006.346878

Cited by 16 publications

(3 citation statements)

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“…The complexity of devices has followed Moores law, and we are now extracting circuits from 45 nm chips. Moreover, these devices now have up to 12 layers of metal, and use an esoteric combination of materials to create both the conductors and dielectrics [2,3]. They may have hundreds of millions of logic gates, plus huge analog, RF, memory, and other macrocell areas.…”

Section: Circuit Extractionmentioning

confidence: 99%

The State-of-the-Art in IC Reverse Engineering

Torrance

James

2009

Lecture Notes in Computer Science

273

132

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Abstract. This paper gives an overview of the place of reverse engineering (RE) in the semiconductor industry, and the techniques used to obtain information from semiconductor products.The continuous drive of Moores law to increase the integration level of silicon chips has presented major challenges to the reverse engineer, obsolescing simple teardowns, and demanding the adoption of new and more sophisticated technology to analyse chips. Hardware encryption embedded in chips adds a whole other level of difficulty to IC analysis. This paper covers product teardowns, and discusses the techniques used for system-level analysis, both hardware and software; circuit extraction, taking the chip down to the transistor level, and working back up through the interconnects to create schematics; and process analysis, looking at how a chip is made, and what it is made of. Examples are also given of each type of RE. The paper concludes with a case study of the analysis of an IC with embedded encryption hardware.

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Section: Circuit Extractionmentioning

confidence: 99%

The State-of-the-Art in IC Reverse Engineering

Torrance

James

2009

Lecture Notes in Computer Science

273

132

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“…The major techniques to introduce uniaxial stress include (i) Embedded SiGe (eSiGe) technology, (ii) Dual Stress Liner (DSL), (iii) Stress Memorization Technique (SMT), and (iv) the parasitic stress from Shallow Trench Isolation (STI). The eSiGe technology embedded SiGe in the source and drain area to introduce compressive stress for PMOS [4]. DSL introduces the stress by depositing a highly stressed silicon nitride layer, tensile stress for NMOS region and compressive stress for PMOS region, over the entire wafer to elevate carrier mobility [4].…”

Section: Introductionmentioning

confidence: 99%

“…The eSiGe technology embedded SiGe in the source and drain area to introduce compressive stress for PMOS [4]. DSL introduces the stress by depositing a highly stressed silicon nitride layer, tensile stress for NMOS region and compressive stress for PMOS region, over the entire wafer to elevate carrier mobility [4]. In SMT, the stress in the channel is transferred from the stressed deposited dielectric and is memorized during the re-crystallization of the active area and poly-gate when thermal annealing is enabled [5].…”

Section: Introductionmentioning

confidence: 99%

Modeling of layout-dependent stress effect in CMOS design

Wang

Zhao

Liu

et al. 2009

Proceedings of the 2009 International Conference on Computer-Aided Design

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Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically captures this behavior is essential to bridge the process technology with design optimization. In this paper, starting from the first principle, a new layout-dependent stress model is proposed as a function of layout, temperature, and other device parameters. Furthermore, a method of layout decomposition is developed to partition the layout into a set of simple patterns for efficient model extraction. These solutions significantly reduce the complexity in stress modeling and simulation. They are comprehensively validated by TCAD simulation and published Si-data, including the state-of-the-art strain technologies and the STI stress effect. By embedding them into circuit analysis, the interaction between layout and circuit performance is well benchmarked at 45nm node.

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Predictive Technology Model of Enhanced CMOS Devices

Cao

2011

Integrated Circuits and Systems

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A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

Cited by 16 publications

References 0 publications

The State-of-the-Art in IC Reverse Engineering

The State-of-the-Art in IC Reverse Engineering

Modeling of layout-dependent stress effect in CMOS design

Predictive Technology Model of Enhanced CMOS Devices

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