A 45nm low power bulk technology featuring carbon co-implantation and laser anneal on 45°-rotated substrate

Blanket SMT With In Situ N2 Plasma Treatment on the $\langle \hbox{100} \rangle$ Wafer for the Low-Cost Low-Power Technology Application

“…However, it requires an extra mask to selectively remove the SMT tensile layer on the PMOS region since the tensilestress liner degrades the hole mobility in PMOS. In low-power technology, the 45d rotated wafer ( 100 orientation on the (100) substrate) has been chosen considering both performance and cost for the following reasons: 1) Intrinsic hole mobility is higher compared to that of a normal wafer, and 2) hole mobility is insensitive to stress, hence the tensile-stress liner can be directly applied on the whole wafer to improve NMOS perfor- mance without degrading PMOS performance, thus reducing the cost [2], [3]. The blanket-SMT process is expected to be implemented on the 45d rotated wafer without degrading PMOS performance.…”