A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on (110)-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy. CMOS devices with physical gate oxide thickness of 1.2nm have been demonstrated, with substantial enhancement of pFET drive current at L,&8Gnm. IntroductionIt is known that hole mobility is more than doubled on (110) silicon substrates with current flow direction along <1 lo> [I -31 compared with conventional (1 00) substrates. However electron mobility is the highest on (100) substrates (Fig. I). To fully utilize the advantage of the carrier mobility dependence on surface orientation, in the present work we have developed a new technology to fabricate CMOS on hybrid substrates with different crystal orientations, with nFETs on silicon of (100) surface orientation and pFETs on (1 IO) surface orientation. High performance CMOS devices using 90nm technology with physical gate oxide thickness as thin as 1.2nm have been demonstrated. Significant pFET enhancement has been achieved.

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