A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Beigné, Edith; Valentian, Alexandre; Miro-Panades, Ivan; Wilson, Robin; Flatresse, Philippe; Abouzeid, Fady; Benoist, T.; Bernard, Christian; Bernard, Sebastien; Billoint, Olivier; Clerc, Sylvain; Giraud, B.; Grover, Anuj; Coz, Julien Le; Noël, Jean-Philippe; Thomas, Olivier; Thonnart, Yvain

doi:10.1109/jssc.2014.2369503

Cited by 43 publications

(21 citation statements)

References 10 publications

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“…Circuits are then suffering from very low throughput even if not is enough energy is available to perform more complex tasks. UTBB FDSOI technology allows finding a compromise between high speed and low leakage as we demonstrated in [4]. This is possible through the use of back biasing voltage as shown in section 3.1 of this paper.…”

Section: Flexibility Requirements For Iot Devicesmentioning

confidence: 97%

“…2(a)) is a high-k metal gate planar technology [4]. There is no channel doping nor pocket implant making the process simpler than bulk and reducing the variability.…”

Section: Utbb Fdsoi Back Biasing For High Flexibilitymentioning

confidence: 99%

“…At technology level, we propose to take advantage of UTBB FDSOI (Ultra Thin Body and Box FDSOI) technology providing a wide range of tunability between high speed and low leakage [4]. Undoped thin-film planar FDSOI is an alternative to bulk devices at the 28nm node and beyond and exhibits an excellent short-channel electrostatic control, low leakage currents and immunity to random dopant fluctuation.…”

Section: Introductionmentioning

confidence: 99%

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UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Berthier

Beigné

Heitzmann

et al. 2016

Solid-State Electronics

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In this paper, we propose to analyze Ultra Thin Body and Box FDSOI technology suitability and architectural solutions for IoT applications and more specifically for autonomous Wireless Sensor Nodes (WSNs). As IoT applications are extremely diversified there is a strong need for flexible solutions at design, architectural level but also at technological level. Moreover, as most of those systems are recovering their energy from the environment, they are challenged by low voltage supplies and low leakage functionalities. We detail in this paper some Ultra Thin Body and Box FDSOI 28nm characteristics and results demonstrating that this technology could be a perfect option for multidisciplinary IoT devices. Back biasing capabilities and low voltage features are investigated demonstrating efficient high speed/low leakage flexibility. In addition, architectural solutions for WSNs microcontroller are also proposed taking advantage of Ultra Thin Body and Box FDSOI characteristics for full user applicative flexibility. A partioned architecture between an Always Responsive part with an asynchronous Wake Up Controller (WUC) managing WSN current tasks and an On Demand part with a main processor for application maintenance is presented. First results of the Always Responsive part implemented in Ultra Thin Body and Box FDSOI 28nm are also exposed.

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Section: Flexibility Requirements For Iot Devicesmentioning

confidence: 97%

“…2(a)) is a high-k metal gate planar technology [4]. There is no channel doping nor pocket implant making the process simpler than bulk and reducing the variability.…”

Section: Utbb Fdsoi Back Biasing For High Flexibilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Berthier

Beigné

Heitzmann

et al. 2016

Solid-State Electronics

Self Cite

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“…The proposed methodology has been validated on two different circuit architectures, namely, a DSP [8] and a RISC processor [9]. Both circuits have been implemented in 28nm FDSOI technology.…”

Section: Applicationmentioning

confidence: 99%

Towards on-line estimation of BTI/HCI-induced frequency degradation

Altieri

Lesecq

Beigné

et al. 2017

2017 IEEE International Reliability Physics Symposium (IRPS)

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“…Furthermore, the introduction of in-situ error-detection, such as Razor [4], [5], and tunable replica circuits with error-detection [6] led to an influx of designs targeted at real-time adjustment for voltage overscaling or over-clocking, according to detected errors [7], [8]. While these innovations have succeeded in pushing margin reduction to the limit, they rely on the capability of the microarchitecture to correct a limited number of errors, for example by replay of instructions.…”

Section: Introductionmentioning

confidence: 99%

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

Constantin

Bonetti

Teman

et al. 2016

ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference

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Abstract-This paper presents DynOR, a 32-bit 6-stage Open-RISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction types currently in flight in the pipeline. To this end, we employ a custom designed clock generation unit, capable of immediate glitch-free adjustments of the clock period over a wide range with fine granularity. Our chip measurements in 28 nm FD-SOI technology show that DynOR provides an average speedup of 19% in program execution over a wide range of operating conditions, with a peak speedup for certain applications of up to 41%. Furthermore, this speedup can be traded off against energy, to reduce the chip power consumption for a typical die by up to 15%, compared to a static clocking scheme based on worst case excitation. I. INTRODUCTIONThe concept of dynamic voltage frequency scaling (DVFS) has been one of the leading approaches to energy-efficient operation for the past twenty years. Furthermore, the introduction of in-situ error-detection, such as Razor [4], [5], and tunable replica circuits with error-detection [6] led to an influx of designs targeted at real-time adjustment for voltage overscaling or over-clocking, according to detected errors [7], [8]. While these innovations have succeeded in pushing margin reduction to the limit, they rely on the capability of the microarchitecture to correct a limited number of errors, for example by replay of instructions.Despite the impressive results and innovative techniques proposed in these and other recent publications, they all adhere to the basic assumption that the clock period must be set according to a global worst-case timing path. However, the study carried out in [9] showed that by applying a nonconventional synthesis strategy to a standard microprocessor core, the longest relevant path for a given pipeline state can vary significantly, depending on the executed instruction types. Therefore, by departing from the conventional global frequency convention and adjusting the clock frequency according to the current pipeline state, margins can be reduced and average throughput and/or energy-efficiency can be improved. In this paper, we present DynOR, a full operational circuit implementing this novel approach, designed and fabricated in a deeply-scaled 28 nm fully-depleted silicon-on-insulator (FD-SOI) technology.Contributions and Outline: The specific contributions of this work are: 1) A dynamic clock adjustment (DCA) technique and corresponding micro-architecture, which enables the trimming of dynamic timing margins occurring in a microprocessor, which results in an increased instruction throughput.2) The first silicon implementation of a microprocessor oper-

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A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Cited by 43 publications

References 10 publications

UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

UTBB FDSOI suitability for IoT applications: Investigations at device, design and architectural levels

Towards on-line estimation of BTI/HCI-induced frequency degradation

DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment

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