A 4Gbps 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control

Jung, Hae-Kang; Lee, Kyung Ho; Kim, Jong-Sam; Lee, Jaejin; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/asscc.2008.4708763

Cited by 3 publications

(6 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This work achieves the data rate of 7.2 Gbps in the tightly coupled microstrip lines on FR4 PCB. Among the CIJ compensation schemes at Tx [7], [8], [12], this work showed the best performance in the jitter reduction. The amount of jitter reduction in [9] is larger than that of this work, because the channel length of [9] is much longer than that of this work (16 in compared with 4 in and 8 in).…”

Section: Resultsmentioning

confidence: 83%

“…12(a) shows the measured Rx jitter versus data rate, without and with the CIJ compensation and in the no-CIJ case (4-in microstrip lines). CIJ depends on the geometry of the coupled transmission line and is independent of data rate [7], [8], [12]. The CIJ values are almost constant at 43.6 3.7 ps for the data rate from 2.6 to 5 Gbps.…”

Section: Resultsmentioning

confidence: 87%

“…Although [6] can be used at the transmitter (Tx), only an Rx implementation is presented. In [7] and [8], the different clock edge timings are applied at Tx for different signal modes by using a mode detector circuit, so that all of the signals with different modes arrive at Rx simultaneously. Because of the mode detector circuit, all three approaches [6]- [8] require relatively large power and chip area.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

Jung

Lee

et al. 2012

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

A single-ended transmitter (Tx) is proposed to compensate for the crosstalk-induced jitter (CIJ) of coupled microstrip lines by subtracting a mimicked crosstalk waveform from data signal at Tx during the data transition time, depending on the data transition of an adjacent line. Since the CIJ component is proportional to the time derivative of data signal, the mimicked crosstalk waveform subtracted at Tx cancels the CIJ at receiver (Rx) for the linearly changing data signal with time. As a by-product, this scheme reduces ISI at Rx. The Tx chip in a 0.13-m CMOS process reduces the total Rx jitter by 96 ps (69%) at 7.2 Gbps (4-in channels) and by 120 ps (72%) at 6 Gbps (8-in channels).

show abstract

Section: Resultsmentioning

confidence: 83%

Section: Resultsmentioning

confidence: 87%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

Jung

Lee

et al. 2012

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

show abstract

“…In the parallel data transmission, crosstalk occurs by the inductive and capacitive couplings between the transmission lines [23]- [25]. Due to the timing jitter of the transmitted parallel data shown in Fig.…”

Section: Sampling Methodsmentioning

confidence: 99%

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Onizawa

Mochizuki

Shirahama

et al. 2014

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

“…Unlike the differential signalling, the signal integrity of a single‐ended signalling directly suffers from the crosstalk among channels. The crosstalk induced jitter (CIJ) may be cancelled at either the receiver or transmitter side .…”

Section: Introductionmentioning

confidence: 99%

Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface

Kim

Yoo

2014

Circuit Theory & Apps

View full text Add to dashboard Cite

SUMMARYFor multi-Gb/s/pin parallel dynamic random access memory (DRAM) interface, a crosstalk cancelling voltage-mode driver is proposed. The voltage-mode driver is composed of a main driver and sub-drivers where the cancellation signal is generated by the sub-drivers. The outputs of the main driver and sub-drivers are combined by a capacitive coupling so the direct current (DC) output swing is not affected by the crosstalk cancellation and the sub-drivers may not consume DC power. The proposed crosstalk cancelling voltage-mode driver implemented in a 0.11-μm complementary metal-oxide semiconductor (CMOS) technology improves the horizontal eye openings by 22.6 ps at 4-Gbps/pin.

show abstract

A 4Gbps 3-bit parallel transmitter with the crosstalk-induced jitter compensation using TX data timing control

Cited by 3 publications

References 0 publications

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Crosstalk cancelling voltage‐mode driver for multi‐Gbps parallel DRAM interface

Contact Info

Product

Resources

About