A 4MHz BW 69dB SNDR continuous-time delta-sigma modulator with reduced sensitivity to clock jitter

Abstract

__ A 3 rd -order 1-bit continuous-time delta-sigma modulator (CTDSM) is reported. By shaping the 1-bit DAC feedback current with the proposed multi-step return-to-zero (RZ) waveform, the CTDSM achieves reduced sensitivity to clock jitter. In addition, the modulator adopts a proposed excess-loop-delay (ELD) compensation scheme. For a 4-MHz bandwidth, the CTDSM achieves a dynamic range of 71.5dB and a peak SNDR of 69 dB. Fabricated in a 0.18-μm CMOS, this chip dissipates 16.9 mW from a 1.8-V supply.