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__ A 3 rd -order 1-bit continuous-time delta-sigma modulator (CTDSM) is reported. By shaping the 1-bit DAC feedback current with the proposed multi-step return-to-zero (RZ) waveform, the CTDSM achieves reduced sensitivity to clock jitter. In addition, the modulator adopts a proposed excess-loop-delay (ELD) compensation scheme. For a 4-MHz bandwidth, the CTDSM achieves a dynamic range of 71.5dB and a peak SNDR of 69 dB. Fabricated in a 0.18-μm CMOS, this chip dissipates 16.9 mW from a 1.8-V supply.

A time-to-digital converter (TDC)-based two-step quantizer is proposed for a multibit continuous-time delta-sigma modulator (CTDSM). In the proposed time-domain quantizer, the barrel-shifting operation realizes the dynamic element matching (DEM) function inherently, eliminating an explicit DEM circuit and the associated circuit latency. The two-step quantization scheme further reduces the hardware and power consumption of a multibit TDC quantizer. A swapper technique, in addition to the inherent DEM, is incorporated to randomize the selection of the two banks of digital-to-analog converter cells, which ensure good linearity. A third-order CTDSM incorporating the proposed TDC-based two-step quantizer is fabricated in a 90-nm CMOS process. The modulator achieves a signal-to-noise-and-distortion ratio of 69.6 dB over a 1-MHz signal bandwidth. Operated from 1.2-V analog and 1-V digital supplies, the whole CTDSM consumes 1.79 mW and achieves a figure of merit of 361 fJ/conversion. Index Terms-Delta-sigma modulator, inherent dynamic element matching (DEM), time-domain quantizer.

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