A 4R2W register file for a 2.3GHz wire-speed POWER&amp;#x2122; processor with double-pumped write operation

This paper details the design of a 64 × 32 bit 4-read 2-write register file in TSMC 65 nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65 nm LP technology. The measured results demonstrate operation of 0.77 GHz, consuming 7.08 mW at 1.2 V, and occupying 0.018 mm 2 .

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“…As for the power efficiency, it shows competitive results with state-of-the-art design for now in [11].…”

Section: Prototype and Measured Resultsmentioning

confidence: 96%

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Han

Zhang

et al. 2012

IEICE Electron. Express

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“…1 composes the 8-read + 4-write register file of a replicated pair of 4-read + 4-write RAMs to reduce the ports from 12 to 8 though the number of cells are doubled. Such replication is widely used for recent processors [3], [12], [15]- [18].…”

Section: Reducing Register File Portsmentioning

confidence: 99%

“…This replication is widely used in recent cores such as the Bulldozer core in Sect. 1 [3], [12], [15]- [18]. Table 3 gives its configuration, which follows modern 8-issue cores such as the IBM POWER7/8, and Intel Haswell and Skylake processors [3]- [6].…”

Section: Baseline Modelmentioning

confidence: 99%

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Yamada

Jimbo

Shioya

et al. 2017

IEICE Trans. Inf. & Syst.

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SUMMARYThe region that includes the register file is a hot spot in high-performance cores that limits the clock frequency. Although multibanking drastically reduces the area and energy consumption of the register files of superscalar processor cores, it suffers from low IPC due to bank conflicts. Our skewed multistaging drastically reduces not the bank conflict probability but the pipeline disturbance probability by the second stage. The evaluation results show that, compared with NORCS, which is the latest research on a register file for area and energy efficiency, a proposed register file with 18 banks achieves a 39.9% and 66.4% reduction in circuit area and in energy consumption, while maintaining a relative IPC of 97.5%.

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“…A number of designs utilize multi-pumping to gain additional access ports while keeping area overhead minimal [6] [7]. The 2.3GHz Wire-Speed POWER processor uses double-pumping to double the writing ports [8].…”

Section: Ram Multi-pumpingmentioning

confidence: 99%

“…The bank replication technique is commonly used in state-of-the-art processing architectures to increase parallelism. The 2.3GHz Wire-Speed POWER processor replicates a 2-read SRAM bank to achieve 4 read ports [8]. Each of the two integer clusters of the Alpha 21264 microprocessor has a replicated 80-entry register file, thus doubling the number of read ports to support two concurrent integer execution units.…”

Section: Multi-read Ram: Bank Replicationmentioning

confidence: 99%

Modular multi-ported SRAM-based memories

Abdelhadi

Lemieux

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Multi-ported RAMs are essential for high-performance parallel computation systems. VLIW and vector processors, CGRAs, DSPs, CMPs and other processing systems often rely upon multi-ported memories for parallel access, hence higher performance. Although memories with a large number of read and write ports are important, their high implementation cost means they are used sparingly in designs. As a result, FPGA vendors only provide dual-ported block RAMs to handle the majority of usage patterns. In this paper, a novel and modular approach is proposed to construct multi-ported memories out of basic dual-ported RAM blocks. Like other multi-ported RAM designs, each write port uses a different RAM bank and each read port uses bank replication. The main contribution of this work is an optimization that merges the previous live-value-table (LVT) and XOR approaches into a common design that uses a generalized, simpler structure we call an invalidation-based live-value-table (I-LVT). Like a regular LVT, the I-LVT determines the correct bank to read from, but it differs in how updates to the table are made; the LVT approach requires multiple write ports, often leading to an areaintensive register-based implementation, while the XOR approach uses wider memories to accommodate the XOR-ed data and suffers from lower clock speeds. Two specific I-LVT implementations are proposed and evaluated, binary and one-hot coding. The I-LVT approach is especially suitable for larger multi-ported RAMs because the table is implemented only in SRAM cells. The I-LVT method gives higher performance while occupying less block RAMs than earlier approaches: for several configurations, the suggested method reduces the block RAM usage by over 44% and improves clock speed by over 76%. To assist others, we are releasing our fully parameterized Verilog implementation as an open source hardware library. The library has been extensively tested using ModelSim and Altera's Quartus tools.

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A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation

Cited by 23 publications

References 3 publications

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS

Skewed Multistaged Multibanked Register File for Area and Energy Efficiency

Modular multi-ported SRAM-based memories

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