A 5–10GHz SiGe BiCMOS FPGA with new configurable logic block

You, Chao; Guo, Jong-Ru; Kraft, R.P.; Chu, Michael; Curran, Peter F.; Zhou, Kun; Goda, Bryan; McDonald, J. F.

doi:10.1016/j.micpro.2004.06.008

Cited by 3 publications

(3 citation statements)

References 6 publications

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“…With a convergence of solid-state qubit coherence times now approaching 1 millisecond [29][30][31] , present day CMOS-based FPGAs or application specific integrated circuits (ASICs) operating at 4 kelvin are a viable control platform. Higher performance control systems that are likely to be realised in the longer term include technologies based on InP devices 32 , SiGe BiCMOS 33,34 , and superconducting flux logic 21 . For the basic demonstration of the PL/AL scheme considered here the classical logic is implemented using a commercial FPGA (Xilinx Spartan-3A) that we have made operational at the 4 K stage of a dilution refrigerator.…”

Section: Cryogenic Logicmentioning

confidence: 99%

Section: Cryogenic Logicmentioning

confidence: 99%

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Cryogenic Control Architecture for Large-Scale Quantum Computing

et al. 2015

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Solid-state qubits have recently advanced to the level that enables them, in principle, to be scaledup into fault-tolerant quantum computers. As these physical qubits continue to advance, meeting the challenge of realising a quantum machine will also require the engineering of new classical hardware and control architectures with complexity far beyond the systems used in today's fewqubit experiments. Here, we report a micro-architecture for controlling and reading out qubits during the execution of a quantum algorithm such as an error correcting code. We demonstrate the basic principles of this architecture in a configuration that distributes components of the control system across different temperature stages of a dilution refrigerator, as determined by the available cooling power. The combined setup includes a cryogenic field-programmable gate array (FPGA) controlling a switching matrix at 20 millikelvin which, in turn, manipulates a semiconductor qubit.Realising the classical control system of a quantum computer is a formidable scientific and engineering challenge in its own right 1,2 . The hardware that comprises the control interface must be fast relative to the timescales of qubit decoherence, low-noise so as not to further disturb the fragile operation of qubits, and scalable with respect to physical resources, ensuring that the footprint for routing signal lines or the operating power does not grow rapidly as the number of qubits increases 3,4 . As solid-state quantum processors will likely operate below 1 kelvin 5-8 , components of the control system will also need to function in a cryogenic environment, adding further constraints.Similar challenges have long been addressed in the satellite and space exploration community 9 , where the need for high-frequency electronic systems operating reliably in extreme environments has driven the development of new circuits and devices 10 . Quantum computing systems, on the other hand, have to date largely relied on brute-force approaches, controlling a few qubits directly via room temperature electronics that is hardwired to the quantum device at cryogenic temperatures.Here we present a control architecture for operating a cryogenic quantum processor autonomously and demonstrate its basic building blocks using a semiconductor qubit. This architecture addresses many aspects related to scalability of the control interface by embedding multiplexing sub-systems at cryogenic temperatures and separating the high-bandwidth analog control waveforms from the digital addressing needed to select qubits for manipulation. Our demonstration comprises a commercial field-programmable gate array (FPGA) operating at 4 kelvin and controlling a microwave signal switching matrix at 20 mK, which then interfaces with a quantum dot device. Bringing these sub-systems together in the context of our control architecture suggests a path for scaleup of control hardware needed to manipulate the large numbers of qubits in a useful quantum machine. I. CONTROL MICRO-ARCHITECTUREOur control micro-...

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Section: Cryogenic Logicmentioning

confidence: 99%

Section: Cryogenic Logicmentioning

confidence: 99%

Cryogenic Control Architecture for Large-Scale Quantum Computing

et al. 2015

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“…This allows it to be an ideal option to be integrated within DNNs. Multiple BiCMOS-based field-programmable gate array (FPGA) modules have been designed [27]- [29]. Hence, a neural network can be modeled on FPGA modules using the proposed XNOR gate.…”

Section: Methodsmentioning

confidence: 99%

A 15-Gbps BiCMOS XNOR gate for fast recognition of COVID-19 in binarized neural networks

Marar

2022

IJECE

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The COVID-19 pandemic is spreading around the world causing more than 177 million cases and over 3.8 million deaths according to the European Centre for Disease Prevention and Control. The virus has devastating effects on economies, health, and well-being of worldwide population. Due to the high increase in daily cases, the available number of COVID-19 test kits in under-developed countries is scarce. Hence, it is vital to implement an effective screening method of patients using chest radiography since the equipment already exists. With the presence of automatic detection systems, any abnormalities in chest radiography that characterizes COVID-19 can be identified. Several artificial-intelligence algorithms have been proposed to detect the virus. However, neural networks training is considered to be time-consuming. Since computations in training neural networks are spent on floating-point multiplications, high computational power is required. Multipliers consume the most space and power among all arithmetic operators in deep neural networks. This paper proposes a 15 Gbps high-speed bipolar-complementary-metal-oxide-semiconductor (BiCMOS) exclusive-nor (XNOR) gate to replace multipliers in binarized neural networks. The proposed gate can be implemented on BiCMOS-based field-programmable gate arrays (FPGAs). This will significantly improve the response time in identifying chest abnormalities in CT scans and X-rays.

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