Jong-Ru Guo scite author profile

This paper describes the implementation of a scalable SiGe FPGA that serves as a high speed FPGA test platform. A new configurable block (Basic Cell) has been evolved from the Xilinx 6200 specification, and is designed to perform in the gigahertz range. Two chips, a 4:1 multiplexer and 1:4 demultiplexer, were designed using the IBM SiGe 7HP process. The two designs can process 10 Gbps data streams.

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A 5–10GHz SiGe BiCMOS FPGA with new configurable logic block

You¹,

Guo²,

Kraft³

et al. 2005

Microprocessors and Microsystems

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Jong-Ru Guo

Selective epitaxial growth of SiGe for strained Si transistors

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology

The 10GHz 4:1 MUX and 1:4 DEMUX implemented via the gigahertz SiGe FPGA

A 5–10GHz SiGe BiCMOS FPGA with new configurable logic block

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