A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process

Abstract

This article presents a high-speed receiver for nextgeneration 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be co-integrated with pixel drivers in the DDI, it must be implemented in a process with high-voltage devices, which poses significant challenges in achieving beyond 5-Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time linear equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180-nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29-dB channel loss while consuming 120 mA from a 1.8-V supply.

A 50Gb/s PAM4 receiver with mid-frequency compensation and decision jitter cancellation

“…However, as the data stream having more than a few hundred of unit intervals (UIs) is transmitted continuously, a long-tailed ISI caused by the mid-frequency loss begins to dominate the datadependent jitter (DDJ) [13]. To solve this issue, [10,14] employed a conventional two-stage CTLE with feedback/ feed-forward high-pass amplifier to compensate for both the mid-frequency and high-frequency loss. However, this approach takes up additional area and power consumption.…”

“…Furthermore, the high-frequency noise is amplified simultaneously during the analog equalization. As a remedy, codesign strategies involving decision feedback equalization (DFE) with superior noise performance were carried out [14,15]. However, the DFE is subject to stringent timing constraints, its feedback time of the first tap must be less than 1 UI [16], where the 𝐶 𝐿𝐾-to-𝑄 delay of slicer dominates the total delay.…”