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This article presents a high-speed receiver for nextgeneration 8K ultra-high-definition TVs. The receiver supports error-free communication between the timing controller and the display driver integrated circuits (DDIs) across various channels. Because the receiver must be co-integrated with pixel drivers in the DDI, it must be implemented in a process with high-voltage devices, which poses significant challenges in achieving beyond 5-Gb/s operation. We propose techniques for overcoming such process-induced speed limitations. They include a level-shifting passive continuous-time linear equalizer (CTLE), an active CTLE with extended bandwidth using a negative capacitor, a speculative decision feedback equalizer with a down-sampled edge-sampling path, and a low-dropout regulator with parallel error amplifiers to achieve all-band power supply rejection. A reference-less clock and data recovery circuit with a new frequency detector is also described. Fabricated in a 180-nm CMOS process, the prototype receiver operates at 5.2 Gb/s and can compensate up to 29-dB channel loss while consuming 120 mA from a 1.8-V supply.

A clock generator using a fast-locking frequency-locked loop (FLL)-based RC oscillator and delta-sigma fractional dividers (FDIVs) to generate programmable temperature-insensitive output frequencies is presented. Successive approximation register (SAR) logic is used to speed up the locking of the FLL, and truncation error cancellation (TEC) is performed in FDIVs to reduce deltasigma-induced jitter. A prototype clock generator fabricated in a 65-nm CMOS process generates output clocks in the range of 1.5-100 MHz with a resolution of 24-kHz, 140-ps peak-to-peak period jitter, 6.8-ppm/ • C inaccuracy, and can be turned on within 20 µs.

This article presents techniques to improve the frequency stability of RC oscillators by performing firstand second-order temperature compensation without needing resistors with opposite temperature coefficients (TCs). Using the proposed three-point digital trim, a prototype 100-MHz frequency-locked loop (FLL)-based RC oscillator fabricated in a 65-nm CMOS process achieves an inaccuracy of ±140 ppm over −40 • C to 95 • C, 83-ppm/V voltage sensitivity, 1.3-ppm Allan deviation floor, and 1-µW/MHz power efficiency. When only a single-point trim is performed using a multiple linear regression model leveraging the strong correlation between three switched resistors, the frequency inaccuracy is ±587 ppm.

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