A 5.4μm2 Stacked Capacitor DRAM Cell with 0.6μm Quadruple-Polysilicon Gate Technology

An optically delineated 4.2- mu m/sup 2/ self-aligned isolated-plate stacked-capacitor DRAM cell

“…Fig. 7 compares the stored charge in the conventional quadruple-STC [3] and the present SISTC both using and not using the PEARL method. Stored charge is estimated assuming a 5-nm SiOz equivalent capacitor film and cell size of 4.2 pm2.…”

“…However, the large alignment tolerance needed to prevent the plate and pad from shorting becomes a major obstacle to cell size reduction. On the other hand, in the quadruple-STC [3], since an Si02 interlayer exists between the storage capacitor and pad, it is not necessary to take the above-mentioned alignment tolerance into consideration when designing this memory cell. Therefore, the quadruple-STC can realize a smaller cell size than the triple-STC.…”

“…INTRODUCTION order to realize highly integrated dynamic random-E ccess memories (DRAM's), it has become necessary to adopt three-dimensional cell structures represented by stacked capacitor cells (STC) [ 11- [3] and trench capacitor cells [4]- [6]. This is because these cells have sufficient storage capacitance (C, ) where conventional planar cells do not.…”