An optically delineated 4.2- mu m/sup 2/ self-aligned isolated-plate stacked-capacitor DRAM cell

Abstract

A 4.2-pm2 stacked capacitor DRAM cell is achieved using conventional i-line photolithography that realizes 0.6-pm pattern delineation. In order to obtain sufficient stored charge for memory operation, self-aligned plate-isolation technology, a novel pattern enlargement method named peripherally added resist lithography (PEARL), and a highly reliable ultrathin capacitor dielectric film are developed. These new technologies enable a stored charge of 25 fF/bit (41 fC/bit) in the present cell. Charge-retention characteristics and alpha-particle immunity are favorable, indicating that this cell is a good candidate for application to 16-Mbit DRAM's.

Embedded DRAM: Technology platform for the Blue Gene/L chip

“…After DT processing, the wafer presents a planar surface and, for all practical purposes, the DT processing can be considered transparent to the rest of the process. This should be contrasted with other processes, such as the stacked capacitor or metalinsulator-metal capacitor (MIM cap) approach, followed by others [11,12] in which the capacitor is created in the middle-of-the-line process (between the device and wiring levels). In the latter case, novel materials must be used, and complex three-dimensional capacitor structures must be built.…”

Device miniaturization and lithography in giga-bit-era DRAMs.

“…3, where all data points refer to ISSCC papers and Qc is the measured critical stored charges against alpha-particle injection [4]. Here, all Qs values exceed 1.5xQc, that is, Qs has a margin of 50% more charges than the Qc.…”