A 5–bit CMOS attenuator with low temperature and process variations for Ka‐band phased‐array applications

Abstract

A 5‐bit CMOS attenuator with low temperature and process variations is presented employing the proposed optimization and compensation technique to achieve low root mean square (RMS) attenuation error and phase variation. The proposed design technique includes optimizing ratio of transistors and attenuation resistors to reduce the temperature and process variations, and utilizing a temperature and process compensation circuitry to further minimize the chip‐to‐chip and channel‐to‐channel variations. The presented attenuator is fabricated in a 55 nm CMOS process and achieves a maximum attenuation of 15.5 dB with 0.5 dB‐per‐step resolution. Measurement results show that the maximum RMS attenuation error is 0.6 dB and phase variation is less than ±2.2°, from −45 to 85°C and between different chips or channels within frequency range from 25 to 32 GHz. The core area is 0.32 × 0.5 mm2 excluding pads.

A high linearity 0.05–7 GHz digital step attenuator with the capacitive compensation for bonding wires parasitic parameters

“…Multiple amplitude compensation methods are implemented to counteract the parasitic parameters of switching transistors, improving the attenuation accuracy and operating bandwidth of the digital step attenuator (DSA). [9][10][11][12][13] However, these designs are for fully integrated on-chip systems, measured by onwafer probing with a near-ideal ground. For the bonding wire package, the reference ground of the chip grounded by the bonding wire is undesirable at high frequencies, which deteriorates the attenuation accuracy and limits the operating bandwidth.…”

“…The efforts in improving the attenuation accuracy of the attenuator were also fruitful. Multiple amplitude compensation methods are implemented to counteract the parasitic parameters of switching transistors, improving the attenuation accuracy and operating bandwidth of the digital step attenuator (DSA) 9–13 . However, these designs are for fully integrated on‐chip systems, measured by on‐wafer probing with a near‐ideal ground.…”