A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider

Rategh, H.R.; Samavati, H.; Lee, T.H.

doi:10.1109/cicc.1999.777334

Cited by 10 publications

(5 citation statements)

References 7 publications

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“…The core of the VCILFD is based on the approach originally proposed in [13,14] and incorporates high-frequency SiGe BJT instead of MOSFET devices. The injected signal is applied to the base of Q 1 and then delivered to the common emitter connection of Q 2 and Q 3 .…”

Section: Circuit Descriptionmentioning

confidence: 99%

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A study of superharmonic injection locking in multiband frequency dividers

Plessas

2011

Circuit Theory & Apps

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SUMMARYA superharmonic voltage-controlled injection-locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross-coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple-band operation is achieved by employing a novel technique that uses pin-diodes and negative power supply. The discrete dividers, built with low noise hetero-junction FETs and high-frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post-layout simulation results of a 5 GHz fully differential injection-locked frequency divider, implemented in a 0.25 m SiGe process are provided.

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Section: Circuit Descriptionmentioning

confidence: 99%

“…Several methods are proposed for injection-locked frequency division operating at gigahertz frequencies [8][9][10][11][12][13][14]. In this work, we present multiband design solutions for frequency division by employing injection locking.…”

Section: Introductionmentioning

confidence: 99%

A study of superharmonic injection locking in multiband frequency dividers

Plessas

2011

Circuit Theory & Apps

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“…As shown in Figure 2, the output nodes Iϩ and IϪ are direct coupled to the gates of Mc3 and Mc4, and the output nodes Qϩ and QϪ are crosscoupled to the gates of Mc2 and Mc1, respectively. It has been shown that both differential VCOs will synchronize to a single oscillation frequency at steady state and quadrature outputs Iϩ, IϪ, Qϩ, QϪ can be generated [7]. The resistances Rs are used to bias the gates of the coupling transistors Mc1-Mc4 and let the gate to source voltages (V gs ) are the same.…”

Section: Circuit Designmentioning

confidence: 99%

A current reused CMOS quadrature injection‐locked frequency divider

Chuang

Jang

Lee

et al. 2007

Micro & Optical Tech Letters

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A fourth-order accurate FDTD scheme with long-time stability, IEEE Microwave Wireless Compon Lett 15 (2005), 271-273. 4. X. Fei and T. Xiaohong, Stability and numerical dispersion analysis of a fourth-order accurate FDTD Method, ABSTRACT: A new current-reused injection-locked frequency divider is proposed to generate quadrature outputs and implemented using the standard UMC 0.18 m CMOS 1P6M process. The proposed circuit is made of two LC-tank voltage controlled oscillators (VCOs) stacked in series and the VCOs are coupled with the coupling transistors to generate quadrature signals. The direct injection-locked technique is applied to the VCO to perform a divide by two functions, so that the quadrature circuit can provide low phase noise signal. At the 1.8 V supply voltage, the free running frequency of proposed circuit operates from 2.3 to 2.63 GHz and provides 1 GHz locking from 4.43 to 5.43 GHz. The power consumption is 7.4 mW with 4.1 mA current consumption. ABSTRACT: In this article, a novel design of printed coplanar waveguide-fed monopole antenna is proposed for triple-band WiMAX applications. At first, we investigate the printed dual-band monopole antenna for dual-band operation with two bands of 2.37-3.64 GHz and Figure 6Measured phase noises of the free-running, external injectionreference and injection-locked signals

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“…The literature reports widespread values of divideby-two locking ranges, e.g., from 12% in [6] to 29% in [7], both of which have been obtained for similar frequencies of oscillation, power supply voltages, power consumptions, and by using very similar ILFD topologies. Such different locking ranges for very similar circuits reveals that: I) the locking range of ILFDs is not necessarily small; II) there is a need for methods to optimize the locking range of ILFDs with respect to their design parameters.…”

Section: Introductionmentioning

confidence: 97%

Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis

Ghahramani

Daneshgar

Kennedy

et al. 2007

2007 18th European Conference on Circuit Theory and Design

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Injection-locked frequency dividers (ILFDs) are versatile analog circuit blocks used, for example, within phase-locked loops (PLLs). With respect to their digital counterparts, they have the advantages of a low power consumption and division ratios greater than two. The price for these advantages is believed to be a limited locking range. Here we show that this is not the case; indeed, by combining nonlinear systems theory (bifurcation analysis) with optimization techniques, we have significantly increased the locking range of a classical (LC oscillator-based) injection-locked frequency divider, predicting a locking range that is about twenty times greater than what has been reported in the literature to date. The wider locking range predicted by the theory has been confirmed by SPICE simulations.

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A 5 GHz, 1 mW CMOS voltage controlled differential injection locked frequency divider

Cited by 10 publications

References 7 publications

A study of superharmonic injection locking in multiband frequency dividers

A study of superharmonic injection locking in multiband frequency dividers

A current reused CMOS quadrature injection‐locked frequency divider

Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis

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