A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure

Westerwick, E.H.

doi:10.1109/vtsa.2001.934525

Cited by 41 publications

(8 citation statements)

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“…The measured NF of a 2.5-turn inductor was compared to the calculated obtained from the measured S-parameters [see (1)], as shown in Fig. 1(a).…”

Section: Resultsmentioning

confidence: 99%

“…In the design of fully on-chip RF low-noise amplifiers (LNAs) for single-chip receiver front-end applications, the minimum NF (NF of the inductors used at the input terminal of the LNAs is crucial for the overall NF performance of the LNAs [1], [2]. This is because the total NF (in dB) of an LNA is usually equal to the NF (or the inverse of maximum available power gain ) of the input inductor plus the NF of the other part of the LNA [3].…”

Section: Introductionmentioning

confidence: 99%

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Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

Lin

2005

IEEE Electron Device Lett.

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In this letter, we analyze the effects of temperature (from 50 C to 200 C) and substrate impedance on the noise figure (NF) and quality factor ( -factor) performances of monolithic RF inductors on silicon. The results show a 0.75 dB (from 0.98 to 0.23 dB) reduction in minimum NF (NF min ) at 8 GHz, an 86.1% (from 15.1 to 28.1) increase in maximum -factor ( max ), and a 4.8% (from 16.5 to 17.3 GHz) improvement in self-resonant frequency ( SR ) were obtained if post-process of proton implantation had been done. This means the post-process of proton implantation is effective in improving the NF and -factor performances of inductors on silicon mainly due to the reduction of eddy current loss in the silicon substrate. In addition, it was found that NF increases with increasing temperature but show a reverse behavior within a higher frequency range. This phenomenon can be explained by the positive temperature coefficients of the series metal resistance ( ), the parallel substrate resistances ( sub1 and sub2 ), and the resistance 1 of the substrate transformer loop. The present analyzes are helpful for RF designers to design less temperature-sensitive high-performance fully on-chip low-noise-amplifiers (LNAs) and voltage-controlled-oscillators (VCOs) for single-chip receiver front-end applications.Index Terms-Noise figure, quality ( ) factor, spiral inductor, substrate impedance, temperature.

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“…The measured NF of a 2.5-turn inductor was compared to the calculated obtained from the measured S-parameters [see (1)], as shown in Fig. 1(a).…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Temperature and substrate-impedance dependence of noise figure of monolithic RF inductors on silicon

Lin

2005

IEEE Electron Device Lett.

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“…7(b) shows the measured stability factor of the proposed LNA. The measured performances of the typical and proposed LNAs are summarized in Table I [7], [8]. Here, the figure of merit (FoM) is calculated as follows [9]:…”

Section: Design Of a Lna Using The Proposed Harmonic Rejection Tmentioning

confidence: 99%

A CMOS LNA Using a Harmonic Rejection Technique to Enhance Its Linearity

Yoon

Park

2014

IEEE Microw. Wireless Compon. Lett.

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In this study, we design a differential low-noise amplifier (LNA) using a 0.18-RF CMOS process. To improve its linearity, we propose a harmonic rejection technique using RC feedback at the gain stage. The third harmonic component of the drain node of the common-gate transistor is fed back to the source node of the common-gate transistor to restrict the generation of the third harmonic component at the output of the LNA. To verify the feasibility of the proposed technique for a linear amplifier, we designed a typical LNA and the proposed LNA in an identical process and with the same design parameters apart from the feedback loop of the proposed LNA. The measured improvement of the input-referred P1 dB of the proposed LNA is approximately 3 dB compared to that of the typical LNA. From these measured results, we successfully prove the feasibility of the proposed linearization technique.

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“…CMOS LNA for use in GPS application and operating at 1.3 GHz and 1.5 GHz input frequencies have been reported in [7] and [8], respectively. CMOS LNA operating at 5 GHz range has been reported in [9]- [10]. A LNA operating at 26-42 GHz has been reported in [11] but it is built on SOI-CMOS process.…”

Section: Introductionmentioning

confidence: 99%