A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

Ramkaj, Athanasios T.; Ramos, Juan Manuel Sánchez; Pelgrom, Marcel; Steyaert, Michiel; Verhelst, Marian; Tavernier, Filip

doi:10.1109/jssc.2019.2960476

Cited by 48 publications

(13 citation statements)

References 18 publications

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“…The ADC is clocked from a single 2 GHz off-chip clock. The clock receiver, which consists of a current-mode logic (CML) stage, a CML-to-CMOS converter, and a CMOS duty-cycle correction block, is utilized to transition the external 2 GHz differential sinusoid to the differential global master clock (GMC) [17]. For TI-ADC, the 8-way interleaved system requires eight 12.5% duty-cycle sampling pulses, which are synchronously generated using an eight-cycle ring counter [10], [18].…”

Section: A Adc Overall Architecturementioning

confidence: 99%

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

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This paper presents an improved correlationbased timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

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Section: A Adc Overall Architecturementioning

confidence: 99%

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Wang

et al. 2022

IEEE Trans. Circuits Syst. I

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“…The temperature estimation function of this type of time domain CMOS temperature sensor is defined as the ratio of two different temperature dependent delay times. The typical structure of this type of temperature sensor, which was proposed by P. Chen et al in 2010 [38], includes two delay lines, of which delay times vary in a different way from each other with respect to temperature, and a successive approximation register (SAR) control logic [76][77][78][79][80][81][82][83][84][85][86][87] implemented as an FSM. For example, if one of these delay lines is composed of the general inverter type delay cells of Figure 5b, then the other is composed of the delay cells shown in Figure 6b which are less sensitive to temperature [33,38].…”

Section: Typementioning

confidence: 99%

Categorization and Characterization of Time Domain CMOS Temperature Sensors

Byun

2020

Sensors

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Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.

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“…Among the several architectural approaches, the SAR-assisted pipeline configurations have been proven a promising high-speed high-resolution ADC structure with excellent energy efficiency [6][7][8][9][10][11][12][13][14][15][16][17]. As shown Figure 1, this type of hybrid ADC uses the low-resolution energy-efficient SAR ADCs and the residue amplifiers (RAs).…”

Section: Introductionmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Electronics

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This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

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A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS

Cited by 48 publications

References 18 publications

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Categorization and Characterization of Time Domain CMOS Temperature Sensors

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

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