A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Ni, Meng; Wang, Xiao; Li, Fule; Rhee, Woogeun; Wang, Zhihua

doi:10.1109/tcsi.2021.3122984

Cited by 21 publications

(8 citation statements)

References 31 publications

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“…• Group 1 (G1): Techniques based on the autocorrelation of the quantized signal [21]- [25]. These techniques are well suited to estimating the sampling time errors, but do not provide information on frequency response mismatches or mismatches affecting different TI-ADCs in the AFE of a QAM receiver.…”

Section: Compensation Requirements and Comparison With The State Of T...mentioning

confidence: 99%

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Solis¹,

Reyes²,

Morero

et al. 2022

IEEE Access

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A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) is presented in this paper. This technique is applicable to equalized digital communication receivers. As shown in the literature, in a digital receiver it is possible to treat the TI-ADC errors as part of the communication channel and take advantage of the adaptive equalizer to compensate them. Therefore calibration becomes an integral part of channel equalization. No special purpose analog or digital calibration blocks or algorithms are required. However, there is a large class of receivers where the equalization technique cannot be directly applied because other signal processing blocks are located between the TI-ADC and the equalizer. The technique presented here generalizes earlier works to this class of receivers. The error backpropagation algorithm, traditionally used in machine learning, is applied to the error computed at the receiver slicer and used to adapt an auxiliary equalizer adjacent to the TI-ADC, called the Compensation Equalizer (CE). Simulations using a dual polarization optical coherent receiver model demonstrate accurate and robust mismatch compensation across different application scenarios. Several Quadrature Amplitude Modulation (QAM) schemes are tested in simulations and experimentally. Measurements on an emulation platform which includes an 8 bit, 4 GS/s TI-ADC prototype chip fabricated in 130nm CMOS technology, show an almost ideal mitigation of the impact of the mismatches on the receiver performance when 64-QAM and 256-QAM schemes are tested. INDEX TERMS Background calibration, error backpropagation, optical coherent receiver, TI-ADC, TI-ADC mismatch calibration. I. INTRODUCTION T HIS paper proposes a novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) used in equalized digital communication receivers. It generalizes a previously proposed technique [1]-[3]. Current and emerging digital receivers for ultra highspeed communication systems [4]-[10] require large bandwidth, high sampling rate ADCs. Please see [11] and references therein for a recent review of interleaving techniques for high speed data converters. The TI-ADC has been the technique predominantly used to meet the demanding sampling rate and bandwidth requirements of high-speed transceivers [12], [13]. The per-formance of TI-ADCs is affected by mismatches among the interleaves [14], [15]. Mismatches of sampling time, gain, bandwidth, as well as DC offset, are the most common impairments. Many calibration techniques have been proposed in the literature. Please see [16]-[41] and references therein for a thorough review and discussion. Calibration techniques for general purpose TI-ADCs in general require dedicated calibration blocks and algorithms. On the other hand, several authors [1]-[3] have shown that in the special case of an equalized digital receiver, it is possible to treat the TI-ADC errors as integral part of the communication channel and take advantage of the already ex...

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Section: Compensation Requirements and Comparison With The State Of T...mentioning

confidence: 99%

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Solis¹,

Reyes²,

Morero

et al. 2022

IEEE Access

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“…Firstly, Equation ( 11) computes the maximum filtered PWM output from Equation ( 10) in logarithmic scale. The filtered PWM output at f PW M is shown in Equation (12).…”

Section: Lpf Parameters For a N-bit Sar-based Adcmentioning

confidence: 99%

“…Most advanced SDRs are able to remove conversion stages to IF, reducing operational amplifiers, filters and other analog elements, using high-performance ADCs (GSPS). The high-performance ADCs are usually implemented on full-custom integrated circuits and use time-interleaving techniques that require several ADCs in parallel to convert the same input [12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

2022

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The flexibility provided by FPGAs permits the implementation of several ADCs, each one configured with the required bit resolution and sampling frequency. The paper presents the design and implementation of scalable and parametrizable analog-to-digital converters (ADC), based on a successive approximation register (SAR), on FPGAs (field programmable gate arrays). Firstly, the work develops a systematic methodology for the implementation of a parametrizable SAR-based ADC from a set of building modules, such as the pulse-width modulator (PWM), external low-pass filter (LPF) and the analog comparator. The presented method allows choosing the LPF parameters for the required performance (resolution bits and sampling frequency) of a SAR-based ADC. Secondly, the paper also presents several optimizations on the PWM module to enhance the sampling frequency of implemented ADCs, and the method to choose the LPF parameters is adapted. The PWM and SAR logic are synthesizable and parametrizable, using a low number of resources, in order to be portable for low-cost FPGA families. The methodology and PWM optimizations are tested on a Zynq-7000 device from Xilinx; however, they can be adapted to any other FPGA.

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“…However, this introduced reference channel will add additional power consumption and area, and affect the input impedance of the TIADC system. In Hamidreza et al, 16 Meng et al 17 and Mingqiang et al, 12 the least mean square (LMS) method is used to accomplish the timing skew detection, but this method has a long estimation time for timing skews. In Kiho et al, 18 Jeonggoo et al, 19 Jianwei et al, 20 and Kiho et al, 21 the window detector (WD) is used to complete timing skew calibrations.…”

Section: Introductionmentioning

confidence: 99%

An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

Zhao

Zhang

et al. 2023

Circuit Theory & Apps

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SummaryA foreground calibration method for timing skews of the time interleaved analog‐to‐digital converter (TIADC) system is proposed in this paper. In this method, the adaptive genetic algorithm (AGA) is used to replace the traditional least mean square (LMS) method to detect the timing skews, and the variable delay lines are used to calibrate the timing skews. This method can accomplish the detection and calibration of positive and negative timing skews, and the reference channels are not required. In addition, compared with other methods, this method has higher detection speed and detection accuracy. In this paper, a four‐channel 18‐bit 1‐GS/s TIADC system is modeled, and the performance of the proposed method is further verified. The results show that the convergence speed and the calibration accuracy of this method are higher, the signal‐to‐noise ratio (SNR) of the TIADC system is improved by 65.9 dB after calibration, and this method is also effective when the frequency of the input signal is close to the Nyquist frequency.

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A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy

Cited by 21 publications

References 31 publications

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Design and Implementation of Scalable and Parametrizable Analog-to-Digital Converter on FPGA

An 18‐bit 1‐GS/s time interleaved analog‐to‐digital converter with timing skew calibration based on an adaptive genetic algorithm

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