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Abstract-This paper presents a new hardware architecture designed for protecting the key of cryptographic algorithms against attacks by side-channel analysis (SCA). Unlike previous approaches already published, the fortress of the proposed architecture is based on revealing a false key. Such a false key is obtained when the leakage information, related to either the power consumption or the electromagnetic radiation (EM) emitted by the hardware device, is analysed by means of a classical statistical method. In fact, the trace of power consumption (or the EM) does not reveal any significant sign of protection in its behaviour or shape. Experimental results were obtained by using a Virtex 5 FPGA, on which a 128-bit version of the standard AES encryption algorithm was implemented. The architecture could easily be extrapolated to an ASIC device based on standard cell libraries. The system is capable of concealing the real key when various attacks are performed on the AES algorithm, using three statistical methods which are based on correlation, the Welch's t-test and the difference of means.Index Terms-Security, side-channel attacks, power analysis attacks, softwarehardware countermeasuresTHE addition of countermeasures for protecting the key in cryptographic algorithms has become an emerging field of research, since in the late 1990s several authors revealed the inherent weakness associated with physical devices used in their implementation [1]. When a cryptographic algorithm is implemented in a hardware device, it could be shown as both its power consumption and its electromagnetic radiation (EM) are heavily dependent on the data that are being processed. Since data rely on the cryptographic key, this dependence can be exploited to find out such a key by using a statistical method of analysis. Further, as the leakage information that is exploited is external to the hardware device, these methods are usually known as Side-Channel Analysis (SCA) attacks.The most widely used statistical method is based on the calculation of the correlation between the captured power trace (or the EM) and a theoretical model of power consumption for a specific key. In order to obtain such a model, it is necessary to know both the data that are being processed and the behaviour of the basic CMOS cells that form the circuit. This model is usually approximated by the Hamming distance (HD) or the Hamming weight (HW) related to the binary value of the particular point to be attacked in the circuit [2]. This approximation is based on the assumption that the actual consumption is proportional to HW or HD. The former represents the number of ones included in a byte vðt k Þ at instant t k , whereas the latter is based on the HW of the result obtained when operating with an exclusive-OR the value of byte v at instants t kÀ1 and t k (i.e., vðt kÀ1 Þ and vðt k Þ). Nevertheless, the knowledge of data is more complicated, since such data depend not only on the plain text to be encrypted but also on the value of the cryptographic key. Generally, it ...

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Abstract-This paper presents the implementation on FPGA of an speaker verification system. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a Vector Floating-Point Unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the microprocessor manages the control of the process and executes the rest of operations. With a clock frequency of 40 MHz, the system is capable of executing in realtime the complete algorithm, processing a voice frame in 9.1 ms. The same verification process was carried out over two different systems: an ARM Cortex A8 microprocessor and configuring MicroBlaze with the scalar Floating-Point Unit provided by Xilinx. Experimental results show that when comparing our proposal against both systems, the number of clock cycles is reduced by a factor of x11.2 and x15.4, respectively. The main advantage provided by the VPFU is its flexibility, which allows quickly adapting the software to the potential changes produced in both the system and the user requirements. The algorithm was tested over a public database, which contains utterances of different users acquired under different environmental conditions, providing good recognition rates.