Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Ramos-Lara, Rafael; López-García, Mariano; Canto-Navarro, Enrique; Puente-Rodriguez, Luís

doi:10.1007/s11265-012-0683-5

Cited by 28 publications

(11 citation statements)

References 16 publications

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“…The architecture of the proposed speaker verification system is well-documented, so it will be briefly reviewed here [18]. Specifically, the block feature extraction is based on the MFCC coefficients, whereas the SVM algorithm is the basis for designing the block creation model and classification.…”

Section: Online Speaker Verification Algorithmmentioning

confidence: 99%

“…In [18], the authors presented a custom-hardware implementation of a speaker verification system. Extrapolating their results for a frequency of 40 MHz, a frame would be processed in 5.8 ms. Other similar proposals are presented in [30] and [31] leading to different results.…”

Section: B Speed Processingmentioning

confidence: 99%

“…• The hardware design presented in [18] is based on fixedpoint arithmetic. Authors achieved high accurate results using a variable word length, whose dimension is adjusted to obtain similar results as those produced in floating-point arithmetic.…”

Section: B Speed Processingmentioning

confidence: 99%

“…Most of these publications proposed the implementation of only one stage, feature extraction or classification, for accelerating the total execution time [14]- [17]. Recently, the work of Ramos et al [18], presented a more advanced implementation of a complete speaker verification system on an FPGA. Authors pointed out that their implementation was able to carry out the feature extraction and classification stages in a shorter time than the frame length (real-time processing).…”

mentioning

confidence: 99%

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Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

Canto-Navarro

López-García

Ramos-Lara

et al. 2015

IEEE Trans. VLSI Syst.

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Abstract-This paper presents the implementation on FPGA of an speaker verification system. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a Vector Floating-Point Unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the microprocessor manages the control of the process and executes the rest of operations. With a clock frequency of 40 MHz, the system is capable of executing in realtime the complete algorithm, processing a voice frame in 9.1 ms. The same verification process was carried out over two different systems: an ARM Cortex A8 microprocessor and configuring MicroBlaze with the scalar Floating-Point Unit provided by Xilinx. Experimental results show that when comparing our proposal against both systems, the number of clock cycles is reduced by a factor of x11.2 and x15.4, respectively. The main advantage provided by the VPFU is its flexibility, which allows quickly adapting the software to the potential changes produced in both the system and the user requirements. The algorithm was tested over a public database, which contains utterances of different users acquired under different environmental conditions, providing good recognition rates.

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Section: Online Speaker Verification Algorithmmentioning

confidence: 99%

Section: B Speed Processingmentioning

confidence: 99%

Section: B Speed Processingmentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

Canto-Navarro

López-García

Ramos-Lara

et al. 2015

IEEE Trans. VLSI Syst.

Self Cite

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show abstract

“…Hardware implementation remains a great challenge that requires tradeoff between accuracy, resource, and computation speed [18,19]. Most of the hardware-based architectures are proposed for speech and speaker recognition using digital signal processor (DSP) [20] or field programmable gate array (FPGA) [21][22][23][24][25][26]. FPGAs are generally preferred to the other hardware approaches because they combine the high-performance of the application-specific integrated circuits (ASICs) and the flexibility of the DSPs.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

Bahoura

2016

Electronics

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Abstract:In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA) using Xilinx System Generator (XSG) and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

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Exploring Text-Constraint Models and Source Information for Long-Enrollment with Short-Test Speaker Verification

Das

Jelil

Prasanna

2018

Circuits Syst Signal Process

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Real-Time Speaker Verification System Implemented on Reconfigurable Hardware

Cited by 28 publications

References 16 publications

Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units

FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

Exploring Text-Constraint Models and Source Information for Long-Enrollment with Short-Test Speaker Verification

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