A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction

Sackinger, E.; Tennen, A.; Shulman, D.; Wani, B.; Rambaud, M.; Lim, D.; Larsen, F.; Moschytz, G.S.

doi:10.1109/jssc.2006.884399

Cited by 15 publications

(5 citation statements)

References 6 publications

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“…In such applications, high linearity, high dynamic range, and low harmonic distortion are important (e.g. ). Obviously, the advantage of this direct method is that it provides simplicity in the circuit architecture, requires no complicated automatic tuning circuitry, and avoids interference of the control signal with the processed signal.…”

Section: Practical Considerationsmentioning

confidence: 99%

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Ladder tuning‐block partitioned filters for simplified tuning

Jurisic

Moschytz

2012

Circuit Theory & Apps

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SUMMARY In this paper, we present a procedure for the design of low‐sensitivity, active‐RC filters that permits efficient functional tuning during the manufacturing process. Filters with finite zeros, such as elliptic (Chebyshev–Cauer) low‐pass filters are primarily considered, although the method can be applied to the design of other filters, e.g. allpole filters, as well. We show how to partition a given ladder filter into two parts. The first is a ladder filter of reduced order compared to the original; the second is a second‐ or third‐order active‐RC filter section, the ‘tuning block’, which, alone is used to tune the overall filter. The ladder, the components of which are fixed, provides most of the selectivity, while the cascaded tuning block determines the band‐edge characteristics and can be tuned relatively easily. A detailed design procedure for the filter partitioning is given. By obtaining a doubly terminated ladder filter, which is cascaded with a tuning block, both the inherent low sensitivity of the ladder and the tunability of the tuning block, are maintained. A Monte Carlo analysis of the partitioned filter demonstrates that the low sensitivity with respect to component tolerances, achievable by maintaining a doubly terminated ladder structure for the larger partitioned part of the filter, is preserved. Copyright © 2012 John Wiley & Sons, Ltd.

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Section: Practical Considerationsmentioning

confidence: 99%

“…Methods of tuning to adjust the frequency response of continuous-time filters are an enduring issue and have already been dealt with by many authors [1][2][3][4][5][6][7][8]. In this paper, we present a new method for low-sensitivity, active-RC filters that simplifies tuning compared to other methods.…”

Section: Introductionmentioning

confidence: 99%

Ladder tuning‐block partitioned filters for simplified tuning

Jurisic

Moschytz

2012

Circuit Theory & Apps

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“…Most recently to combat the low Q's and lossy problems, they have been constructed using active gyrator-C circuits in CMOS [5][6][7]. Usually when combined with filters, filtering typically precedes the transformer to shape or band-limit signals, as used in xDSL systems, the most common example being the filters in splitters for ADSL/POTS systems [8][9][10][11]. However, filters are rarely built around magnetic transformers with a few attempts in the literature [12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Second order bandstop and bandpass filters using transformers

Maundy

Elwakil

2015

Microelectronics Journal

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“…The CMOS design is the most promising, efficient, and good enormous trade-off solution in term of circuit miniaturization. So far, various classical electronic functions as amplifier [3][4], low-voltage signal processor [5], several aspects of filters [6][7][8][9][10][11][12][13][14], PLL [15], transconductors [16], were designed in CMOS technology are available in the literature. Design method of CMOS amplifier with precise and stable DC gain was introduced [3][4].…”

mentioning

confidence: 99%

“…The expected advantages of CMOS technology are the low-power consumption [5][6] and compact [7] circuit design. One of most expanded circuit designs are expected for filters with different characteristics as continuous time [6,9], log-domain [7], AC-powered [8], nanometer technology [10][11][12], enhanced adaptive, Q-tuning scheme [13] and high dynamic range [14] filters. Despite the development of the CMOS design technology of analog circuit, the designability of certain unfamiliar analog functions as the low-pass (LP) negative group delay (NGD) circuits [17][18][19][20] remain one of open questions.…”

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confidence: 99%

Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology

Wan

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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This paper introduces an innovative design of a low-pass (LP) negative group delay (NGD) integrated circuit (IC) in 180-nm CMOS technology. The LP-NGD circuit is an inductorless topology constituted by RC-network with CMOS metal-insulator-metal (MIM) capacitor and poly gate resistor. The design methodology is illustrated by considering the chip layout process. Then, the first run simulation is performed with the design rule check (DRC) and 2.5 mm × 2.2 mm layout versus schematic (LVS) approaches. The feasibility of the CMOS LP-NGD IC circuit implementation is validated with chip-on-board (CoB). The proof of concept (PoC) of the LP-NGD miniaturized circuit was tested in both S-parameter and time-domain. As expected, the calculated, simulated and experimented results of CoB showing NGD of about -10 ns over 12 MHz and -10 dB attenuation is confirmed. Moreover, time-domain investigations were also performed to show the feasibility of generating pulse and arbitrary waveform signal time-advance through the designed and fabricated LP-NGD CoB prototypes.

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A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction

Cited by 15 publications

References 6 publications

Ladder tuning‐block partitioned filters for simplified tuning

Ladder tuning‐block partitioned filters for simplified tuning

Second order bandstop and bandpass filters using transformers

Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology

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