A 5-V-only 16-Mb flash memory with sector erase mode

Jinbo, T.; Nakata, H.; Hashimoto, Kohji; Watanabe, T.; Ninomiya, Keiken; Urai, T.; Koike, M.; Sato, Taichiro; Kodama, Noriyuki; Oyama, Kenichi; Okazawa, T.

doi:10.1109/4.165335

Cited by 34 publications

(4 citation statements)

References 7 publications

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“…[1][2][3] It can be used to fabricate many novel structures, such as triple well, retrograde well, and retrograde well with buried layer. 1,2,[4][5][6] These structures can be fabricated to optimize many device characteristics almost independently, such as channel mobility, punch-through voltage, junction capacitance, latchup susceptibility, soft-error immunity, etc., by employing multiple high-energy ion implantation. [1][2][3] However, there is a concern about the high-energy ion implantation regarding the secondary defects in the substrates that are formed during the postimplantation thermal annealing process.…”

mentioning

confidence: 99%

Detection of the Defects Induced by Boron High-Energy Ion Implantation of Silicon

Hsu

Chen

Liang

2000

J. Electrochem. Soc.

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A preferential chemical etching method was used to investigate the secondary defects induced in silicon by high-energy boron ion implantation followed by a rapid thermal anneal at 1000ЊC for 30 s in N 2 ambient. The dislocation defects in silicon can be clearly delineated by the etchant of CrO 3 /HF mixing solution. Moreover, a band of striation corresponding to the region of dislocation defects can be observed from the cross-sectional view micrographs of scanning electron microscopy. For the high-energy boron ion implantation at a dose of 3 ϫ 10 14 cm Ϫ2 and energies of 0.5 to 2 MeV studied in this work, the defect density is estimated to be in the order of 6 ϫ 10 6 cm Ϫ2. Furthermore, we found a close correlation between the depth profiles of the observed etching pits and that of the implantation-induced damage.

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mentioning

confidence: 99%

Detection of the Defects Induced by Boron High-Energy Ion Implantation of Silicon

Hsu

Chen

Liang

2000

J. Electrochem. Soc.

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“…[12][13][14][15] Figures 3(a) and 3(b) show the four-phase charge pump. [16][17][18][19] The threshold voltage (V TH ) loss of MOS diodes is reduced by boosting the gate of MOS diodes. Row decoder the power efficiency or the output voltage, V OUT .…”

Section: Problems Of the Conventional Charge Pump Circuitmentioning

confidence: 99%

A 1.2 V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized Threshold Voltage at Each Pump Stage for Ferroelectric-NAND Flash Memories

Noda¹,

Hatanaka²,

Miyaji³

et al. 2010

Jpn. J. Appl. Phys.

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Excimer laser projection patterning with an ArF (193 nm) source has been employed in the irradiation of thin diamond films. The effect of a number of process parameters including laser fluence and processing ambient on the quality of the etch product has been investigated; scanning electron microscopy shows that good control of etch quality may be achieved with excellent lateral reproduction of images down to 2 µm. Raman scattering and Auger electron spectroscopy of irradiated films have been correlated, and modifications in the diamond surface have been quantified according to processing parameters. Electrical tests on laser modified surfaces show that the reactivities of metals have a major role in the performance of contact metallizations on such a material. The viability of excimer laser etching of diamond as a manufacturing technique is considered.

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“…6 for highly parallel search operations. In contrast to commonly used sense amplifiers, which consist of two current-voltage converters and a voltage-differential amplifier [8], ours is a latch-type current-differential amplifier. Because it contains no current mirror amplifier, power dissipation is quite low.…”

Section: A Search Sense Amplifiermentioning

confidence: 99%

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

Miwa

Yamada

Hirota

et al. 1996

IEEE J. Solid-State Circuits

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This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 m 2 and a die size of 42.9 mm 2 have been achieved with 0.8 m design rules. Read access time and search access time are 115 ns and 145 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access.

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A 5-V-only 16-Mb flash memory with sector erase mode

Cited by 34 publications

References 7 publications

Detection of the Defects Induced by Boron High-Energy Ion Implantation of Silicon

Detection of the Defects Induced by Boron High-Energy Ion Implantation of Silicon

A 1.2 V Power Supply, 2.43 Times Power Efficient, Adaptive Charge Pump Circuit with Optimized Threshold Voltage at Each Pump Stage for Ferroelectric-NAND Flash Memories

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

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