2021
DOI: 10.1109/lssc.2020.3041236
|View full text |Cite
|
Sign up to set email alerts
|

A 5-V-Program 1-V-Sense Anti-Fuse Technology Featuring On-Demand Sense and Integrated Power Delivery in a 22-nm Ultra Low Power FinFET Process

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
2
1

Citation Types

0
4
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
6

Relationship

1
5

Authors

Journals

citations
Cited by 6 publications
(4 citation statements)
references
References 3 publications
0
4
0
Order By: Relevance
“…The LRS/via-fusing resistance ratio is at least ∼10 8 at 0.1 V (similar resistance ratio with anti-fuse or conventional metal-fuse). 43 Noted the device went to high currents during the higher RESET voltage sweep is classified as the "dielectric breakdown (DB)," which is the irreversible LRS. Figure 4a shows the yield in three operations for OTP memory on the self-selective memory as a function of temperature (298 K-423 K).…”
Section: Resultsmentioning
confidence: 99%
“…The LRS/via-fusing resistance ratio is at least ∼10 8 at 0.1 V (similar resistance ratio with anti-fuse or conventional metal-fuse). 43 Noted the device went to high currents during the higher RESET voltage sweep is classified as the "dielectric breakdown (DB)," which is the irreversible LRS. Figure 4a shows the yield in three operations for OTP memory on the self-selective memory as a function of temperature (298 K-423 K).…”
Section: Resultsmentioning
confidence: 99%
“…The LRS/fusing resistance ratio is at least ∼10 6 at 0.1 V (similar resistance ratio with A-F or metal-fuse). 1,2 Figure 2a shows the MIM via-fusing yield for five tested devices with various via areas. Yield is 100% for 0.16 μm 2 and decreasing with via area increasing (coefficient of determination, R-square: 0.74), which indicates that the area scaling can improve yield and is suitable for CMOS scaling trend.…”
Section: Resultsmentioning
confidence: 99%
“…While eFuse technology supports lower program voltages, AF technology has traditionally promised better density and security. 1,2 In addition, the emerging memristive technologies as called ReRAM (resistive random-access memory), have shown that both advanced CMOS node implementation (beyond 14 nm FeFET) and capability for multilevel cell (MLC) application (enabling the flexibility of weighting modulation as synaptic device) by precise electrical control of the filament growth. 3,4 This opens an opportunity for embedded memory and further applications, 5 e.g., neuromorphic computing, which takes inspiration from the high parallelism in the human brain, low power, high speed, and noise-tolerant computing capabilities.…”
mentioning
confidence: 99%
“…Polysilicon is utilized as the fuse element in prior CMOS technologies before utilizing the high-k metal gate in the front-end technology (Chen et al, 2017;Cheng et al, 2018;Doi et al, 2020;Chen et al, 2021). With high demands on computing configurations, the logic process-compatible non-volatile OTP utilizing the resistive memory is critical for recent applications, namely, security for data storage, security, Internet of Things, and modern system-on-chip (Kulkarni et al, 2021;Liu et al, 2018;Okuno et al, 2020;Shamsoshoara et al, 2020;Yang et al, 2020). This results in challenges, such as, increase in the fuse bit counts, overall area, large power consumption, and reliability.…”
Section: Introductionmentioning
confidence: 99%