A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs

Hussein, Ahmed I.; Vasadi, Sriharsha; Paramesh, Jeyanandh

doi:10.1109/jssc.2017.2746669

Cited by 35 publications

(9 citation statements)

References 39 publications

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“…It should be noted that only a few papers report fractional spur levels at mmW frequencies. In [8], the spur levels appear to have been incorrectly taken from PN plots without accounting for the resolution BW. In [10], with the sophisticated DTC nonlinearity calibration, a lower fractional spur of −38 dBc (normalized to 60 GHz) was achieved.…”

Section: Resultsmentioning

confidence: 99%

“…However, those techniques cannot be easily migrated to fractional-N PLLs, where the loop components contribute significant noise. A 60-GHz fractional-N all-digital PLL (ADPLL) with a fine-resolution (450 fs) time-to-digital converter (TDC) was introduced in [8] to achieve low IPN. Again, with a high FREF of 100 MHz and power-hungry fine-resolution TDC, the PLL BW was set to >2 MHz to suppress the oscillator PN.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong

Chen

Staszewski

2019

IEEE J. Solid-State Circuits

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In this paper, we propose a 60-GHz fractional-N digital frequency synthesizer aimed at reducing its phase noise (PN) at both the flicker (1/f 3) and thermal (1/f 2) regions while minimizing its power consumption. The digitally controlled oscillator (DCO) fundamentally resonates at 20 GHz and co-generates a strong third harmonic at 60 GHz which is extracted to the output while canceling the 20-GHz fundamental. The latter component is fed back to the frequency dividers in an all-digital phase-locked loop for phase detection, which comprises a pair of digital-to-time and time-to-digital converters with dithering to attenuate fractional spurs. The mechanism of flicker noise upconversion to 1/f 3 PN in the DCO is investigated, and a reduction technique is proposed. The 28-nm CMOS prototype achieves 213-277-fs rms jitter in the 57.5-67.2-GHz tuning range while consuming only 40 mW. The DCO flicker PN corner is record low at 300-400 kHz.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Zong

Chen

Staszewski

2019

IEEE J. Solid-State Circuits

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“…Measuring a time interval is a necessary step in various applications such as chemical sensors readout [1], biosensors [2], frequency synthesizers [3][4][5][6] and all-digital phase-locked loops (ADPLLs) [7] which is generally performed by time-todigital converters (TDCs). Whether Nyquist rate or oversampling operation, TDCs critical performance parameters such as linearity, dynamic range and resolution are the main concern of designers to be improved [8][9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of a Multirate 5-bit High-Order 52 fs_rms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

et al. 2021

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This paper describes FPGA implementation of a high-order continuous-time multi-stage noiseshaping (MASH) ΔΣ time-to-digital converter (TDC). The TDC is based on Gated Switched-Ring Oscillator (GSRO) and employs multirating technique to achieve improved performance over conventional ΔΣ TDCs. The proposed TDC has been implemented on an Altera Stratix IV FPGA development board. Dynamic and static tests were performed on the proposed design and experimental results demonstrate that it can perform its function without the need of calibration. The built-in clock circuitries of the FPGA board provides sampling clocks and operating frequencies of the GSROs. This work presents a 52 fsrms, 89.7 dB dynamic range and 0.18 ps time-resolution at 200 MHz, 800 MHz, 1600 MHz sampling rate at the first, second and third stage, respectively, which demonstrate that the proposed third-order TDC can play an important role in applications such as ADPLLs and range finders in which accuracy and speed are vital.

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“…In many applications such as all-digital phase-locked loops (ADPLLs) [1], chemical sensors readout [2], frequency synthesizers [3][4][5][6], and time-of-flight (ToF) systems [7], time-to-digital converters (TDCs) play an important role by measuring a time interval. Thus far, many TDCs have been presented which have been trying to show high signal-to-noise ratio (SNR), resolution, bandwidth, and linearity.…”

Section: Introductionmentioning

confidence: 99%

“…Estimated integrated noise ( Resolution 2 /12) 2. Estimated resolution ( T int,rms 2 .12) 3. FPGA core power consumption 4.…”

mentioning

confidence: 99%

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

et al. 2019

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An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved.

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A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs

Cited by 35 publications

References 39 publications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Design and Analysis of a Multirate 5-bit High-Order 52 fs_rms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

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A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs

Cited by 35 publications

References 39 publications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

A Low-Noise Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications

Design and Analysis of a Multirate 5-bit High-Order 52 fsrms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA

An FPGA-Based 16-Bit Continuous-Time 1-1 MASH ΔΣ TDC Employing Multirating Technique

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Product

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Design and Analysis of a Multirate 5-bit High-Order 52 fs_rms Δ ∑ Time-to-Digital Converter Implemented on 40 nm Altera Stratix IV FPGA