A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction

Jiang, Wenlong; Hokhikyan, Vahagn; Chandrakumar, Hariprasad; Karkare, Vaibhav; Marković, Dejan

doi:10.1109/jssc.2016.2624989

Cited by 114 publications

(47 citation statements)

References 31 publications

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“…State-of-the-art methods for mitigating the indirect artefact try to prevent saturation of the front ends. Saturation can be prevented by increasing the amplifier linear input range and tolerance to d.c. current offset 21,26,46 , or by subtracting the large amplitude components of the artefact 47,48 . Artefact duration can be reduced by rapidly clearing charge built up on circuit elements from stimulation 25,26,49,50 .…”

Section: System Designmentioning

confidence: 99%

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

et al. 2018

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losed-loop neuromodulation improves open-loop therapeutic electrical stimulation by providing adaptive, on-demand therapy, reducing side effects and extending battery life in wireless devices 1,2. Closing the loop requires low-latency extraction and accurate estimation of neural biomarkers 3-5 from recorded signals to automatically adjust when and how to administer stimulation as feedback to the brain. Recent studies have shown responsive stimulation to be a viable option for treating epilepsy 2,6 , and there is evidence that closed-loop strategies could improve deep brain stimulation (DBS) for treating Parkinson's disease and other motor disorders 7,8. However, there is presently no commercial device allowing closed-loop stimulation for DBS in patients with movement disorders, and strategies for implementing such stimulation are still under investigation. In fact, most attempts to close the loop for DBS treatments have been done only for short duration using systems that were not fully implantable 4,5,9-11. To enable advanced research in closed-loop neuromodulation, there is a need for a flexible research platform, for testing and implementing these various closed-loop paradigms, that is also wireless, compact, robust and safe. Designing such a device requires unification of multi-channel recording, biomarker detection and microstimulation technologies into a single unit with careful consideration of their interactions. Wireless, multi-channel recording-only devices capture activity from wide neuronal populations 12,13 , but do not have the built-in ability to immediately act on that information and deliver stimulation. Several complete closed-loop devices have been proposed and demonstrated, but are limited by low channel counts 14-17 and low wireless streaming bandwidth 14-18. Most recently, variations of the fully integrated and optimized closed-loop neuromodulation system-on-a-chip (SoC) have been presented, but full system functionality has not yet been adequately demonstrated in vivo 19-25. While future versions may be paired with miniaturized external battery packs and controllers, current systems built around these SoCs require large, stationary devices to deliver power inductively from a close range 19,21,23. This limits studies to using small, caged animals. Furthermore, any device for concurrent sensing and stimulation must be able to mitigate or remove stimulation artefactsthe large voltage transients resulting from stimulation that distort recorded signals and obscure neural biomarkers. Signals recorded concurrently with stimulation may contain relevant information for closed-loop algorithms or offline analysis, yet existing devices disregard these affected windows of data, or fail to reduce artefacts to an acceptable level for recovery of many potentially useful biomarker features. Effectively and efficiently cancelling artefacts requires careful co-design of the stimulators and signal acquisition chains. Additionally, computational reprogrammability is needed for application-dependent algorithm de...

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Section: System Designmentioning

confidence: 99%

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

et al. 2018

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“…For neural recording AFEs there already exists a great wealth of designs in the literature [5], [9], [19]- [35]. In brief, the key design considerations we have taken here include: 1) Open or closed loop: Closed-loop topologies typically utilise pseudo resistors (realized by diode-connected MOSFET pairs): (1) provide DC feedback [19] and/or (2) define the passive RC corner frequency [20], [21]. The feedback network is used to precisely define the gain and dynamic range.…”

Section: A Analogue Front-end (Afe)mentioning

confidence: 99%

“…Subsequent gain stages utilising capacitive feedback amplifiers provide additional gain and filtering function. On the other hand, open loop configurations (in either the analogue [22]- [24] or frequency [21] domain) aim to reduce complexity and improve power efficiency. Open loop topologies however, require digital calibration for linearity (due to dynamic range limitations), and advanced CMOS technology node for minimising silicon area.…”

Section: A Analogue Front-end (Afe)mentioning

confidence: 99%

A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput

Liu

Luan

Williams

et al. 2017

IEEE Trans. Biomed. Circuits Syst.

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Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low-noise (2.1 V), low-power (23 W per analogue channel) neural recording system-on-chip (SoC). This features individually configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth, and sampling rate settings can be independently configured to extract local field potentials at a low data-rate and/or action potentials (APs) at a higher data rate. The sampled data are streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve 2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting coprocessor to provide a real-time (low latency) output. The system has been implemented in a commercially available 0.35-m CMOS technology occupying a silicon area of 19.1 mm (0.3 mm gross per channel), demonstrating a low-power and efficient architecture that could be further optimized by aggressive technology and supply voltage scaling.

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“…Ideally, in a differential measurement, two identical electrodes should cancel-out their half-cell potentials [15]. In practice, a random differential electrode offset, up to hundred millivolts, can appear [4], [13], [16], [17]. Moreover, the situation is worsened when the recording functionality is combined with the brain stimulation, where a build-up of charge occurs between electrodes [18]- [20], as well as undesired in-band stimulation artifacts [16], [17].…”

Section: Introductionmentioning

confidence: 99%

“…Although the aforementioned techniques are effective for rejecting the electrode offset in traditional neural recording interfaces, a different approach is needed for brain stimulation systems. In particular, neural recording interfaces with a high effective-number-of-bits (ENOB>12-bit) are needed to linearly capture the ECoG signal in the presence of large stimulation artifacts, without saturating the readout architec-ture [16], [17]. However, even these interfaces still rely on the aforementioned offset rejection techniques.…”

Section: Introductionmentioning

confidence: 99%

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

Ivanisevic

Rodriguez

Rusu

2018

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 µm CMOS triple-well process and has a total power consumption of 54 µW. Measurement results, across ten packaged samples, show approximately 14-ENOB over a 300 Hz bandwidth with an input referred noise of 5.23 µVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

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A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction

Cited by 114 publications

References 31 publications

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

A wireless and artefact-free 128-channel neuromodulation device for closed-loop stimulation and recording in non-human primates

A 64-Channel Versatile Neural Recording SoC With Activity-Dependent Data Throughput

A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems

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