A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

Suzuki, Kazumasa; Yamashina, M.; Nakayama, Takashi; Izumikawa, M.; Nomura, Masahiro; Igura, H.; Heiuchi, H.; Goto, J.; Inoue, Toshiaki; Koseki, Yoshiyuki; Abiko, H.; Okabe, E.; One, A.; Yano, Y.; Yamada, H.

doi:10.1109/4.340419

Cited by 23 publications

(3 citation statements)

References 8 publications

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“…Ignoring process variation, the skew of this network is zero as all branches and drivers are equivalently sized. In most microprocessor designs, process variation is accounted for by inclusion of device variation only (e.g., deviations in effective channel length) [45]. Due to the large wirelengths seen in clock trees, the impact of back-end process variation may not be negligible.…”

Section: General Methodologymentioning

confidence: 99%

Analytical modeling and characterization of deep-submicrometer interconnect

Sylvester

Wu²

2001

Proc. IEEE

149

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This work addresses two fundamental concepts regarding deepsubmicrometer interconnect. First, characterization of on-chip interconnect is considered with particular attention to ultrasmall capacitance measurement and in-situ noise evaluation techniques. An approach to measuring femto-Farad level wiring capacitances is presented that is based on the concept of supplying and removing charge with active devices. The method, called the charge-based capacitance measurement (CBCM) technique, has the advantages of being compact, having high-resolution, and being very simple. We also present a novel time-domain measurement scheme for on-chip crosstalk noise that is based on the use of cascaded high-speed differential pairs to compare a user-defined reference voltage to the unknown noise peak value. The noise measurement technique complements a delay measurement to directly evaluate the impact of capacitive coupling on delay for various victim and aggressor driver sizes as well as arbitrary waveform timing and phase alignments. The second area of emphasis in this work is analytical interconnect modeling. Several important effects are modeled, including a rigorous crosstalk noise model that also includes a timing-level model. Results from this noise model show it to provide accuracy within 10% of SPICE for a wide range of input parameters. The noise model can also be calibrated and verified with comparison to the noise measurement scheme described in this work. A fast Monte Carlo approach to modeling the circuit impact of back-end process variation is presented, providing a better depiction of real 3performance spreads compared to the traditional skew-corner approach. Finally, a comprehensive system-level performance model called Berkeley Advanced Chip Performance Calculator (BACPAC) is developed that accounts for a number of relevant deep-submicrometer system design issues. BACPAC has been implemented online and is useful in exploring the capabilities of future very large scale integration systems as well as determining trends and tradeoffs inherent in the design process.

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Section: General Methodologymentioning

confidence: 99%

Analytical modeling and characterization of deep-submicrometer interconnect

Sylvester

Wu²

2001

Proc. IEEE

149

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“…The performance of data processing per unit time, that is, throughput, is an important factor for applicationspecific integrated circuits (ASICs). In real-time processing LSIs for telecommunications and/or moving-picture encoders, a high-frequency clock and/or wide-bit I/O configuration are employed to enhance the throughput [1,2]. Thus, high operating frequency with low power dissipation is in great demand for the SRAMs used in these ASICs.…”

Section: Introductionmentioning

confidence: 99%

Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers

Shibata

Morimura

1999

Electron. Comm. Jpn. Pt. II

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High‐performance SRAM macrocells used in the MPEG2 video‐encoding LSI chip sets are described. In designing 13 kinds of SRAMs with different sizes, size‐configurable memory architecture is employed to shorten design turnaround time. Input and output registers are embedded in the SRAMs for reducing output delay and the timing margin in the presence of skews between input signals. The increase of access time in the read cycle following a writing cycle is suppressed by avoiding overcharging bitlines during the writing‐recovery time. In order to reduce recovery time and power dissipation, sense amplifiers and wordlines are inactivated during the writing‐ recovery time. A redundant address‐decoding scheme is also proposed to reduce the number of unnecessarily activated memory cells when a wordline is selected. A 4K‐word × 24‐bit SRAM test chip is fabricated with a 0.5‐μm CMOS process. The chip demonstrates 200‐MHz operation under 3.3‐V, 25 °C typical conditions and achieves low power dissipation of 110 mW at the 81‐MHz operating frequency used in the MPEG2 video‐encoding LSI chip sets. © 1999 Scripta Technica, Electron Comm Jpn Pt 2, 82(1): 1–10, 1999

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“…When we do Monte Carlo simulations (Section 6) we will incorporate the inter-buffer skew which will give us an accurate estimate of the total power dissipation in the mesh. In the design of top-level tree, stage connect clock tree approach of [14] can be used to reduce the skew which will result in lesser inter-buffer skew at the mesh. (Table IV).…”

Section: Short Circuit (Sc)mentioning

confidence: 99%

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

Reuben

Zackriya.V

Nashit

et al. 2013

IEICE Electron. Express

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Tree driven mesh is gaining popularity as a viable method to distribute clock with minimum skew in Deep Sub Micron (DSM) technology. In the design of the leaf level mesh, the density of the mesh at various parts of the chip is a crucial factor which decides the clock skew and power dissipated in the mesh. We propose a capacitance driven mesh formation methodology which forms a minimum wire length, non-uniform mesh when compared to the traditional skewdriven mesh. After connecting the sinks to the mesh by a combination of Steiner tree and stubs, appropriately sized buffers are placed at optimal locations such that skew and power dissipation are minimized. When our algorithms were tested on ISPD2010 benchmarks, the power dissipated in the mesh was found to be 25% lesser and the skew was 32% to 45% lesser than the skew driven mesh.

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A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

Cited by 23 publications

References 8 publications

Analytical modeling and characterization of deep-submicrometer interconnect

Analytical modeling and characterization of deep-submicrometer interconnect

Size-configurable 200-MHz low-power SRAM macrocells for MPEG2 video-encoding LSIs: Performance enhancement with embedded registers

Capacitance driven clock mesh synthesis to minimize skew and power dissipation

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