A 50nm high-k poly silicon gate stack with a buried SiGe channel

Jakschik, S.; Hoffmann, T.; Cho, H.-J.; Veloso, A.; Loo, Roger; Sorada, Haruyuki; Inoue, A.; Potter, M. de; Eneman, G.; Severi, S.; Absil, P.; Biesemans, S.

doi:10.1109/vtsa.2007.378905

Cited by 2 publications

(2 citation statements)

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“…Si 1-x Ge x -channels for p-type transistors have been demonstrated before: several versions of high-hole mobility transistors (HHMT) and more conventional Si 1-x Ge x -channel pFETs have been fabricated by various groups [6][7][8]. Nowadays, Si 1-x Ge x -channel pFETs receive renewed attention because of their compatibility with high-k/metal gate technologies: for silicon channels it is difficult to reach the desired threshold voltage (V T ) at low Equivalent Oxide Thickness (EOT) for high-performance technologies using highk/metal gates.…”

Section: Introductionmentioning

confidence: 99%

Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Eneman¹,

Hellings²,

Mitard³

et al. 2011

ECS Trans.

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Si1-xGex-channel pFETs can combine enhanced intrinsic performance with a threshold voltage shift, therefore this technology possibly facilitates the use of high-k/metal gate stacks in high-performance applications. This review presents imec's work on a new device concept using Si1-xGex-channels, the implant-free quantum well transistor, that can additionally provide improved short-channel scalability, as well as further performance enhancement when compared to conventional silicon and Si1-xGex-channel pFETs. Furthermore, circuit simulations of Si1-xGex-channel pFETs indicate that this technology shows even more enhanced potential at reduced supply voltages, and also in circuits that allow operation at lower electric fields such as stacked transistors. Finally it is demonstrated that the layout sensitivity of Si1-xGex-channel pFETs is an important concern, especially for variations of the device width. The effectiveness of another stress technique, Si1-xGex Source/Drain, is shown to be decreased when used in combination with Si1-xGex-channel pFETs.

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Section: Introductionmentioning

confidence: 99%

Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Eneman¹,

Hellings²,

Mitard³

et al. 2011

ECS Trans.

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“…Besides the approaches based on epitaxial deposition, silicon nitride Contact Etch Stop Layers (CESLs) [1] and Stress Memorization Techniques (SMT) [2] have become common methods used by the integrated circuits industry to induce stress in the channel of MOS devices. Furthermore, new promising channel devices such as SiGe or Ge-channel pMOSFETs [4,5] are currently being investigated as potential candidates to extend the CMOS technology below the 22 nm node.…”

Section: Introductionmentioning

confidence: 99%

Elastic Relaxation Evaluation in SiGe/Si Hetero-Epitaxial Structures

González¹,

Naka

Hikavyy³

et al. 2011

ECS Trans.

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In this paper, the impact of downscaling the geometry on the stress levels of SiGe/Si hetero-epitaxial structures is investigated by two different experimental techniques, i.e., Raman spectroscopy and High-Resolution X-ray diffraction analysis. The experimental results are complemented by finite element stress simulations. It is shown that the lowest stress levels are obtained for window sizes lower than 5 μm wide, and moreover, for a larger epitaxial thickness. As is discussed, this dependence is connected with elastic relaxation at the edges of the SiGe epilayers.

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A 50nm high-k poly silicon gate stack with a buried SiGe channel

Cited by 2 publications

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Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Elastic Relaxation Evaluation in SiGe/Si Hetero-Epitaxial Structures

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A 50nm high-k poly silicon gate stack with a buried SiGe channel

Cited by 2 publications

References 0 publications

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Elastic Relaxation Evaluation in SiGe/Si Hetero-Epitaxial Structures

Contact Info

Product

Resources

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Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques