Si_1-xGe_x-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Abstract

Si1-xGex-channel pFETs can combine enhanced intrinsic performance with a threshold voltage shift, therefore this technology possibly facilitates the use of high-k/metal gate stacks in high-performance applications. This review presents imec's work on a new device concept using Si1-xGex-channels, the implant-free quantum well transistor, that can additionally provide improved short-channel scalability, as well as further performance enhancement when compared to conventional silicon and Si1-xGex-channel pFETs. Furthermore, circuit simulations of Si1-xGex-channel pFETs indicate that this technology shows even more enhanced potential at reduced supply voltages, and also in circuits that allow operation at lower electric fields such as stacked transistors. Finally it is demonstrated that the layout sensitivity of Si1-xGex-channel pFETs is an important concern, especially for variations of the device width. The effectiveness of another stress technique, Si1-xGex Source/Drain, is shown to be decreased when used in combination with Si1-xGex-channel pFETs.

(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

“…The combination of a Si 1-x Ge x channel and Si 1-y Ge y source/drain leads to interactions between the two stressed layers, especially when the channel layer is etched out during the source/drain recess: this in general leads to a reduced effectiveness of the Si 1-y Ge y source/drain module for higher germanium concentrations in the channel (19). As a consequence, for short channels and high Ge concentrations in the channel, a raised source/drain module will generate more stress in the channel than a recessed module, as shown in Figure 9.…”

“…This width dependence can be mitigated by the stress from the source/drain module, depending on the concentration of the source/drain and channel regions (14,16). On the other hand, the effectiveness of Si 1-y Ge y S/D stressors is reduced for IFQW-FETs, due to elastic relaxation of the channel during the source/drain recess etch (19). The purpose of this work is to provide a general overview of stressor effects in Si/Ge IFQW pFETs.…”

(Invited) Implant Free SiGe-Quantum Well: From Device Concept To High-Performing pFETs

“…Particularly for the case of device width scaling, this can lead to elastic relaxation of the perpendicular stress component, which is the component running along the width of the device. Stress simulations focusing on this dependency (not shown here but extensively investigated in [18,19]) confirm that part of this component gets relaxed near the STI interface, even without formation of defects.…”

Si1-yGey or Ge1-zSnz Source/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

“…Si 1Àx Ge x -channel pFETs can be used to further enhance the performance of CMOS technology. Properties of Si 1Àx Ge x -channel pFETs are: improved scalability due to the quantum-well band offset between channel and substrate, [1][2][3] enhanced mobility due to the use of a highlystrained channel, 1,[3][4][5][6][7] further performance enhancement for narrow-width transistors due to uniaxial-compressive channel stress, 8,9) compatibility with other stressors like Si 1Ày Ge y source/drain (S/D), leading to reduced layout dependence, 10) and superior negative-bias temperature instability due to the channel's favorable valence band offset. [11][12][13] The combination of a strained channel and a S/D stressor leads to a different optimization than for silicon-channels: whereas for Si-channels the recess depth of the S/D module needs to be maximized to obtain the highest stress, for Si 1Àx Ge x -channels, less recess may lead to higher final channel stress, especially for short channels.…”