Si_1-yGe_y or Ge_1-zSn_z Source/Drain Stressors on Strained Si_1-xGe_x-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

Abstract

The interaction between two stress techniques, strain-relaxed buffers (SRBs) and epitaxial source/drain stressors, is studied on short, Si1-x Ge x - and Ge-channel planar transistors. This work focuses on the longitudinal channel stress generated by these two techniques. Unlike for unstrained silicon-channel transistors, for strained channels on top of a strain-relaxed buffer a source/drain stressor without recess generates similar longitudinal channel stress than source/drain stressors with a deep recess. The least efficient stress transfer is obtained for source/drain stressors with a small recess that removes only the strained channel, not the substrate underneath. These trends are explained by a trade-off between elastic relaxation of the strained-channel during source/drain recess and the increased stress generation of thicker source/drain stressors. For Ge-channel pFETs, GeSn source/drains and Si1-x Ge x strain-relaxed buffers are efficient stressors for mobility enhancement. The former is more efficient for gate-last schemes than for gate-first, while the stress generated by the SRB is found to be independent of the gate-scheme.

Processing Technologies for Advanced Ge Devices

“…12,13 A major challenge is to maintain the material quality. To avoid strain relaxation of the channel and surface reflow of the uncovered S/D areas, surface treatments at elevated temperatures should be avoided.…”

“…Source/drain contact layers.-In case of strained channels on top of a SRB, the additional longitudinal stress created by source/drain stressors is very similar irrespective of the presence of a prior S/D recess. 12,13 A major challenge is to maintain the material quality. To avoid strain relaxation of the channel and surface reflow of the uncovered S/D areas, surface treatments at elevated temperatures should be avoided.…”

“…11 A carefully designed epitaxial Source/Drain contact allows to increase the uni-axial strain in the channel, although it needs to be taken into account that this strain engineering technique becomes less efficient with reducing device dimensions especially the contact to poly pitch. 12,13 This resulted in a renewed interest in the use of SiGe SRBs as virtual substrate for the introduction of compressive stress in the Ge channel. Figure 1 shows a typical example of a strained Ge p-type FinFET device.…”

“…1,2,4,6,15,19,20 The process flow also contains the epitaxial growth of the Source/Drain contacts to increase the uni-axial strain in the channel, although this strain engineering technique becomes less efficient with reducing device dimensions. 12,13 Reduced device dimensions set also a clear need to reduce the S/D contact resistivity as this might limit device performance. 21,22 The STI last approach enables to fabricate devices with a lower defect density in the active part of the device.…”

Comparison between experimental and simulated strain profiles in Ge channels with embedded source/drain stressors

“…The most straightforward approach is to replace the silicon channel by a so-called high-mobility channel material, like Si 1-x Ge x , Ge or Ge 1-y Sn y [17]. However, in order to surpass the device performance of strained-silicon channels, additional strain engineering will be necessary for boosting the device performance beyond the 10 nm technology requirements [18][19][20]. To develop optimized stressors for future technology nodes, TCAD-based strain simulations are a very helpful tool [21].…”