(Invited) Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Abstract

Novel device architectures offer improved scalability but come often at the price of increased layout sensitivity and a reduced or changed effectiveness of stressors and gate-last integration schemes. This work focuses on stress effects in n-type FinFETs and p-type Si1-xGex-channel pFETs, and relies mainly on TCAD results. It will be shown that on n-FinFETs, tensile stressed Contact Etch-Stop Layers (t-CESL) are less effective than on planar FETs when a gate-first scheme is used. For gate-last schemes, CESL is as effective as on planar FETs, moreover a strong boost is expected when compared to gate-first schemes. Tensile stressed gates are shown to be an effective stressor on gate-first n-FinFETs, but not on gate-last: in the latter case a slight mobility degradation is predicted. For pFETs with strained Si1-xGex-channels like the Implant-Free Quantum Well (IFQW) FET, it will be shown that elastic relaxation during source/drain recess is an important factor that reduces the effectiveness of Si1 yGey source/drain stressors. For scaled technologies, omitting the source/drain recess altogether and opting for a raised source/drain scheme is preferred. In IFQW pFETs, dependence of the drive current on transistor width is an important concern. It will be shown that a Si1 yGey source/drain reduces the layout dependence of IFQW FETs, an effect that is enhanced further when combined with a gate-last integration scheme.

Germanium Based Field-Effect Transistors: Challenges and Opportunities

“…Additionally, it is strongly favorable to use the same material system for both n -channel and p -channel devices (either Ge for both, or for example, InGaAs for both) since this substantially simplifies device processing [ 4 , 5 ]. Due to the exceptionally high μ h of Ge, and the progress made in Ge based p -channel MOSFETs (pMOSFETs) [ 6 – 14 ] and p -channel quantum well FETs (pQWFETs) [ 2 , 15 – 19 ] over the last decade, there appears to be a consensus in the device research community and in industry that Ge offers the best option for PMOS devices [ 1 , 2 , 20 ]. In light of this, there is heightened incentive to develop Ge based NMOS devices that perform comparably.…”

Si1-yGey or Ge1-zSnz Source/Drain Stressors on Strained Si1-xGex-Channel P-Type Field-Effect Transistors: A Technology Computer-Aided Design Study

“…Si 1Àx Ge x -channel pFETs can be used to further enhance the performance of CMOS technology. Properties of Si 1Àx Ge x -channel pFETs are: improved scalability due to the quantum-well band offset between channel and substrate, [1][2][3] enhanced mobility due to the use of a highlystrained channel, 1,[3][4][5][6][7] further performance enhancement for narrow-width transistors due to uniaxial-compressive channel stress, 8,9) compatibility with other stressors like Si 1Ày Ge y source/drain (S/D), leading to reduced layout dependence, 10) and superior negative-bias temperature instability due to the channel's favorable valence band offset. [11][12][13] The combination of a strained channel and a S/D stressor leads to a different optimization than for silicon-channels: whereas for Si-channels the recess depth of the S/D module needs to be maximized to obtain the highest stress, for Si 1Àx Ge x -channels, less recess may lead to higher final channel stress, especially for short channels.…”

(Invited) Stress Simulations of Si- and Ge-Channel FinFETs for the 14 nm-Node and Beyond

“…For several stressors, design parameters like gate length and pitch have a strong influence (1,2): decreasing gate length and spacer width allows bringing the S/D stressor and CESL closer to the gate leading to higher mobility, while scaling down the gate pitch squeezes out these stressors from the source/drain regions leading to lower effectiveness. Finally, the stress generated by S/D stressors and CESL depends on the elastic properties of the gate stack (3), and is most effective for gate-last technologies (4,5).…”

“…The increased topography of FinFET architectures can lead to more complicated channel stress profiles and unexpected mobility enhancement / degradation when comparing to planar technologies (5,6). In particular, scaling the fin pitch does not have an obvious equivalent in planar technologies, and leads to increased transversal channel stress for gate stressors and enhanced effectiveness of S/D stressors due to merging of epi layers from neighboring fins (6).…”

“…While previous work has focused on stressors in isolated fins (5)(6)(7)(8), this work studies how stressors behave in aggressively scaled, gate-last bulk FinFET technologies for the 14 nm-node and beyond. Both Si-and Ge-channels, and n-and pFET stressors are considered in nested fins with a scaled gate and fin pitch.…”