A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS

Qazi,; Stawiasz,; Chang,; Chandrakasan,

doi:10.1109/isscc.2010.5433818

Cited by 22 publications

(15 citation statements)

References 5 publications

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“…There are a number of SRAM design solutions to address above scaling challenges, including different layout topologies for the 6 T cells [22,23] and new cell design utilizing more transistors per cell, for example, 8 T and 10 T cells [24,25].…”

Section: Sram Scalingmentioning

confidence: 99%

Memory Technologies: Status and Perspectives

Zhirnov

Marinella

2014

Emerging Nanoelectronic Devices

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Section: Sram Scalingmentioning

confidence: 99%

Memory Technologies: Status and Perspectives

Zhirnov

Marinella

2014

Emerging Nanoelectronic Devices

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“…While low-swing signaling enables more dynamic energy savings as voltage swing decreases, the process variation effect worsens. Based on 1000-run Monte-Carlo Spice simulations, we chose 300mV-swing for above 3-σ reliability, but the voltage swing can be further decreased by offset compensation circuit techniques [1,19,22] at the cost of design complexity. Appendix C delves into further evaluation of our low-swing datapath.…”

Section: Low-swing Signalingmentioning

confidence: 99%

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Park

Krishna

Chen

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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In this paper, we present a case study of our chip prototype of a 16-node 4x4 mesh NoC fabricated in 45nm SOI CMOS that aims to simultaneously optimize energy-latency-throughput for unicasts, multicasts and broadcasts. We first define and analyze the theoretical limits of a mesh NoC in latency, throughput and energy, then describe how we approach these limits through a combination of microarchitecture and circuit techniques. Our 1.1V 1GHz NoC chip achieves 1-cycle router-and-link latency at each hop and energy-efficient router-level multicast support, delivering 892Gb/s (87.1% of the theoretical bandwidth limit) at 531.4mW for a mixed traffic of unicasts and broadcasts. Through this fabrication, we derive insights that help guide our research, and we believe, will also be useful to the NoC and multicore research community.

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“…27 Not only does the worst-case delay of the true 1 decrease, but also the separation between true 1 and false 1 widens and preserves a sampling window at 0.55 V for 90% yield of a 64-Kbyte array. The ACSA works by storing the variable threshold of the amplifying PMOS M3 in series with the BL signal while also suppressing the variation of the output PMOS M4 by driving its gate-to-source voltage at a rate equal to (1 þ g m r o ) times the BL signal development, where g m is the transconductance of M3, and r o is the output resistance of M3.…”

Section: Future Landscape Of Embedded Memoriesmentioning

confidence: 99%

Challenges and Directions for Low-Voltage SRAM

Qazi

Sinangil

Chandrakasan

2011

IEEE Des. Test. Comput.

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SRAM IS THE most common embedded-memory option for CMOS ICs. As the supply voltage of lowpower ICs decreases, it must remain compatible with the operating conditions. At the same time, increasingly parallel architectures of such low-power systems demand more on-chip cache to effectively share information across parallel processing units. Finally, supply voltage scaling improves the energy consumed by SRAM and dramatically reduces its leakage power.Achieving low-voltage operation in SRAM faces a confluence of challenges, originating from process variation, and related to bit cell stability, sensing, architecture, and efficient CAD methodologies. The trend toward increased quantity of embedded SRAM in scaled technology compounds the specific need of SRAM in low-power systems. Integrating more memory on chip provides an effective means to use silicon because of memory's lower power density, layout regularity, and performance and power benefits from reduced off-chip bandwidth. As a result, the everincreasing integration of embedded SRAM continues. 2 By employing some of the design innovations discussed in this article, this memory design minimizes energy per access and achieves a 50Â reduction in leakage power by trading off performance. Indeed, low-power systems benefit from SRAMs that function at very low voltage in the state of the art, but such design solutions of lowvoltage SRAM significantly impact area and performance. 3 Reducing this area overhead and further improving the metrics of energy per accessed bit and leakage power will enable new opportunities for low-power electronics in mobile platforms. Wearable electronics, portable medical monitors, and implantable medical devices are some of the applications requiring the storage of significant quantities of information (e.g., patient data), low-access energy caches, and a long operating lifetime from a battery.In this article, we discuss the challenges to embedded-SRAM design, with particular emphasis on the factors that limit the minimum operating supply voltage V min . We also explore various design solutions and discuss open areas of investigation. ChallengesThe workhorse of embedded memory is SRAM based on the 6T (six-transistor) cell, shown in Figure 2a. From this cell, a subarray is assembled by tiling memory cells into a grid with wordlines (WLs) running horizontally and bitlines (BLs) running vertically, as in Figure 3. Each memory cell is associated with one or more WLs and one or more BLs. Nominally, the bit cell supplies and well biases are globally connected to static voltage sources. During read, the WL voltage V WL is raised, and the memory cell discharges either BLT (bitline true) or BLC (bitline complement), depending on the stored data on nodes Q and bQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs return to the positive supply rail. During write, V WL is raised and the BLs are forced to Future Landscape of Embedded MemoriesEditor's note: SRAMs capable of operating a...

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A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS

Cited by 22 publications

References 5 publications

Memory Technologies: Status and Perspectives

Memory Technologies: Status and Perspectives

Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI

Challenges and Directions for Low-Voltage SRAM

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