SRAM IS THE most common embedded-memory option for CMOS ICs. As the supply voltage of lowpower ICs decreases, it must remain compatible with the operating conditions. At the same time, increasingly parallel architectures of such low-power systems demand more on-chip cache to effectively share information across parallel processing units. Finally, supply voltage scaling improves the energy consumed by SRAM and dramatically reduces its leakage power.Achieving low-voltage operation in SRAM faces a confluence of challenges, originating from process variation, and related to bit cell stability, sensing, architecture, and efficient CAD methodologies. The trend toward increased quantity of embedded SRAM in scaled technology compounds the specific need of SRAM in low-power systems. Integrating more memory on chip provides an effective means to use silicon because of memory's lower power density, layout regularity, and performance and power benefits from reduced off-chip bandwidth. As a result, the everincreasing integration of embedded SRAM continues. 2 By employing some of the design innovations discussed in this article, this memory design minimizes energy per access and achieves a 50Â reduction in leakage power by trading off performance. Indeed, low-power systems benefit from SRAMs that function at very low voltage in the state of the art, but such design solutions of lowvoltage SRAM significantly impact area and performance. 3 Reducing this area overhead and further improving the metrics of energy per accessed bit and leakage power will enable new opportunities for low-power electronics in mobile platforms. Wearable electronics, portable medical monitors, and implantable medical devices are some of the applications requiring the storage of significant quantities of information (e.g., patient data), low-access energy caches, and a long operating lifetime from a battery.In this article, we discuss the challenges to embedded-SRAM design, with particular emphasis on the factors that limit the minimum operating supply voltage V min . We also explore various design solutions and discuss open areas of investigation.
ChallengesThe workhorse of embedded memory is SRAM based on the 6T (six-transistor) cell, shown in Figure 2a. From this cell, a subarray is assembled by tiling memory cells into a grid with wordlines (WLs) running horizontally and bitlines (BLs) running vertically, as in Figure 3. Each memory cell is associated with one or more WLs and one or more BLs. Nominally, the bit cell supplies and well biases are globally connected to static voltage sources. During read, the WL voltage V WL is raised, and the memory cell discharges either BLT (bitline true) or BLC (bitline complement), depending on the stored data on nodes Q and bQ. A sense amplifier converts the differential signal to a logic-level output. Then, at the end of the read cycle, the BLs return to the positive supply rail. During write, V WL is raised and the BLs are forced to
Future Landscape of Embedded MemoriesEditor's note: SRAMs capable of operating a...
