A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS

Jia, Haikun; Ma, Ruichang; Deng, Wei; Wang, Zhihua; Chi, Baoyong

doi:10.1109/isscc42614.2022.9731581

Cited by 15 publications

(6 citation statements)

References 7 publications

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“…Poor PN and low resonating frequencies make ring oscillators unsuitable for mm-wave applications. Operating oscillators at 2× frequency followed by a ÷2 divider is a suitable solution but only in the sub-6-GHz bands since doubling the operating frequency in mm-wave oscillators worsens the PN significantly [14], [15], [16]. Recently, a PPF seems to be a promising scheme for mm-wave I/Q generation [17], [18], [19], [20] since it would barely degrade the LO's PN.…”

Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90 • I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140-250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors' knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

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Section: Table I Specifications Of Irr and Its Corresponding Evmmentioning

confidence: 99%

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Chen

Siriburanon

et al. 2023

IEEE J. Solid-State Circuits

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“…[95,96] show that a mode-rejected multi-core topology favors the mm-wave operation compared with resistance-coupled multi-core because the slab topology inductors in the mode-rejected topology can achieve a very small inductor (~20 pH) with considerably high Q (>25). The reported phase noise and FoM of the 60 GHz quad-core [95] and 16core [96] oscillators are -104.7 and 186.5 dBc/Hz, and -111.1 and 185.7 dBc/Hz at 1 MHz offset, respectively. The multicore oscillator draws more current from the power supply, thus lowering the phase noise.…”

Section: Voltage-controlled Oscillatorsmentioning

confidence: 99%

Trending IC design directions in 2022

Chan¹,

Cheng²,

Deng³

et al. 2022

J. Semicond.

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For the non-stop demands for a better and smarter society, the number of electronic devices keeps increasing exponentially; and the computation power, communication data rate, smart sensing capability and intelligence are always not enough. Hardware supports software, while the integrated circuit (IC) is the core of hardware. In this long review paper, we summarize and discuss recent trending IC design directions and challenges, and try to give the readers big/cool pictures on each selected small/hot topics. We divide the trends into the following six categories, namely, 1) machine learning and artificial intelligence (AI) chips, 2) communication ICs, 3) data converters, 4) power converters, 5) imagers and range sensors, 6) emerging directions. Hope you find this paper useful for your future research and works.

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“…However, low-frequency oscillator has large chip area, and the multiplying stage inevitably costs extra power consumption and area. Another method to obtain low phase noise is multi-core oscillator [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29]. According to Lesson's phase noise equation [30], it is possible for an N -core oscillator to burn N times higher power and decrease the phase noise by 10 log(N ).…”

Section: Introductionmentioning

confidence: 99%

“…According to Lesson's phase noise equation [30], it is possible for an N -core oscillator to burn N times higher power and decrease the phase noise by 10 log(N ). Differing from conventional parallel connected multi-core oscillators based on extra coupling circuit, the circular-type multi-core oscillators [25], [26], [27], [28], [29] are attractive for high area efficiency. Compared with mm-wave single-core oscillators [31], [32], whose inductors may suffer the destructive coupling between traces, the larger diameter of the circular-type oscillator helps to obtain a higher quality factor.…”

Section: Introductionmentioning

confidence: 99%

“…Compared with mm-wave single-core oscillators [31], [32], whose inductors may suffer the destructive coupling between traces, the larger diameter of the circular-type oscillator helps to obtain a higher quality factor. However, once the core number is increased, complex supply and decoupling networks are required [29]. The unavoidable parasitics in supply and ground paths have adverse impact on the performance.…”

Section: Introductionmentioning

confidence: 99%

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Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance

Shu,

Luo

2023

IEEE J. Solid-State Circuits

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In this article, a scalable inter-core-shaping multicore oscillator is proposed to achieve low phase noise and high figure of merit (FoM) at millimeter-wave (mm-wave) band. Adjacent NMOS and PMOS cores generate common-mode (CM) resonance simultaneously, but with opposite signs; thus, differential capacitors can be used to create resonance at twice the oscillation frequency. Such a CM resonance limits flicker noise upconversion and reduces phase noise. The capacitors in differential mode (DM) and CM are all differential, which avoids the degradation of quality factor caused by the single-end capacitor. Besides, the magnetic coupling among the cores only operates in DM. In CM, the negative and positive mutual couplings cancel each other, which increases the CM inductance and its quality factor. Moreover, the topology shows low sensitivity to the parasitics in the return path and the mismatch among the cores, which makes it suitable for the massive-core extension. The 28-GHz quad-core and 20-core circuits are prototyped in a conventional 40-nm CMOS process. Occupying a core area of 0.06 mm 2 , the quad-core oscillator achieves 1-MHz FoM of 193.3 dBc/Hz. The 20-core circuit exhibits 1-MHz phase noise of −120.8 dBc/Hz at 28 GHz and 1-MHz FoM of 192.7 dBc/Hz. Index Terms-Figure of merit (FoM), figure-of-merit area (FoM A ), inter-core shaping, low phase noise, millimeter wave (mm wave), multi-core, oscillator.

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A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS

Cited by 15 publications

References 7 publications

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain–Gate–Source for Low Flicker Phase Noise and I/Q Exactness

Trending IC design directions in 2022

Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance

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