A 56-Gb/s Optical Receiver With 2.08-μA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology

Dziallas, Giannino; Fatemi, Adel; Pęczek, Anna; Zimmermann, Lars; Malignaggi, Andrea; Kahmen, Gerhard

doi:10.1109/tmtt.2021.3104838

Cited by 14 publications

(5 citation statements)

References 20 publications

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“…Using monolithic integration, the split-MRR resonant photodetector has a data rate of 12 Gb/s with 0.58 pJ/bit energy efficiency based on CMOS technology [118], and a 56 Gb/s optical receiver with 3.66 pJ/bit energy efficiency is implemented based on BiCMOS technology [119]. Closed-loop thermal tuning for MRR-filter is also necessary for wavelength locking of MRR-based receivers.…”

Section: Statusmentioning

confidence: 99%

Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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Due to the rise of 5G, IoT, AI, and high-performance computing applications, datacenter traffic has grown at a compound annual growth rate of nearly 30%. Furthermore, nearly three-fourths of the datacenter traffic resides within datacenters. The conventional pluggable optics increases at a much slower rate than that of datacenter traffic. The gap between application requirements and the capability of conventional pluggable optics keeps increasing, a trend that is unsustainable. Co-packaged optics (CPO) is a disruptive approach to increasing the interconnecting bandwidth density and energy efficiency by dramatically shortening the electrical link length through advanced packaging and co-optimization of electronics and photonics. CPO is widely regarded as a promising solution for future datacenter interconnections, and silicon platform is the most promising platform for large-scale integration. Leading international companies (e.g., Intel, Broadcom and IBM) have heavily investigated in CPO technology, an inter-disciplinary research field that involves photonic devices, integrated circuits design, packaging, photonic device modeling, electronic-photonic co-simulation, applications, and standardization. This review aims to provide the readers a comprehensive overview of the state-of-the-art progress of CPO in silicon platform, identify the key challenges, and point out the potential solutions, hoping to encourage collaboration between different research fields to accelerate the development of CPO technology. Graphical Abstract

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Section: Statusmentioning

confidence: 99%

Co-packaged optics (CPO): status, challenges, and solutions

Tan

Liu³

et al. 2023

Front. Optoelectron.

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“…While an automatic gain control is also implemented, the manual gain was used throughout the later experiments. Further information on the circuit design may be found in [21]. The power consumption of the output stage is 450 mW.…”

Section: B Electrical Output Stagementioning

confidence: 99%

Multiband Silicon Photonic ePIC Coherent Receiver for 64 GBd QPSK

Seiler¹,

Voigt²,

Pęczek

et al. 2022

J. Lightwave Technol.

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Multiband coherent communication is being handled as a promising candidate to address the increasing demand for higher data rates and capacity. At the same time, coherent communication is expected to enter the data center domain in the near future. With coherent data links in both, data-and telecom, spanning multiple optical bands, novel approaches to coherent transceiver design and traffic engineering will become a necessity. In this work, we present a monolithically integrated silicon photonic coherent receiver for O-and C-band. The receiver features a 2 × 2 multi-mode interference coupler network as 90 • hybrid optimized for 1430 nm (E-band). The total power consumption is 460 mW at a footprint of approximately 6 mm 2 , and an opto-electrical bandwidth of 33 GHz. 64 GBd operation is demonstrated in O-and C-band, which is competitive to the state-of-the-art for silicon photonic coherent receiver in the Cband, and the highest symbol rate to date for O-band coherent communication.

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“…Prior monolithic literature with both a transmitter and receiver on-wafer demonstrated links at up to 25 Gbps [22][23][24] with published simulation models for a monolithic die at 106 Gbps [25]. Prior individual monolithic results (i.e., only a transmitter or only a receiver) demonstrate a transmitter at 44 Gbps NRZ [26], a receiver at 56Gbps NRZ [27], and a coherent receiver at up to 66 Gbaud QPSK [28], all in a SiGe BiCMOS-SiPh monolithic process; as well as a 100 Gbps PAM4 transmitter [29], a 56 Gbps PAM4 transmitter [30], and separately a 28 Gbps NRZ receiver [31] in a CMOS-SiPh process.…”

Section: Introductionmentioning

confidence: 97%

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

Baehr-Jones,

Ardalan,

Chang

et al. 2023

Preprint

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We demonstrate a transmitter and receiver in a silicon photonics platform for O-band optical communication that monolithically incorporates a modulator driver, traveling-wave Mach-Zehnder modulator, control circuitry, photodetector, and TIA in the GlobalFoundries Fotonix™ (45SPCLO) platform. The transmitter and receiver show an open 112 Gbps PAM4 eye at a 4.3 pJ/bit energy efficiency, not including the laser. Extensive use of gain-peaking enables our modulator driver and TIA to achieve the high bandwidths needed in the 45 nm CMOS-silicon photonics process. Our results suggest an alternative to the frequent approach of bump-bonding BiCMOS drivers and TIAs to silicon photonics.

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A 56-Gb/s Optical Receiver With 2.08-μA Noise Monolithically Integrated into a 250-nm SiGe BiCMOS Technology

Cited by 14 publications

References 20 publications

Co-packaged optics (CPO): status, challenges, and solutions

Co-packaged optics (CPO): status, challenges, and solutions

Multiband Silicon Photonic ePIC Coherent Receiver for 64 GBd QPSK

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

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