A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

Yi, Xiaoke; Boon, Chirn Chye; Liu, Hang; Lin, Jiao; Lim, Wei Meng

doi:10.1109/jssc.2013.2293021

Cited by 100 publications

(36 citation statements)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our PLL has the lowest RMS jitter and the lowest in-band phase noise. The other PLL that reaches a jitter value that is close ( [23] ) has a lower power consumption, but does not include any LO buffer, which we include such that this PLL can be used as a part of a direct-conversion 60 GHz TRX. Further, our PLL uses a static divider that covers the output frequency of the QVCO and does not need calibration unlike injection locked solutions [31].…”

Section: Resultsmentioning

confidence: 99%

“…The topologies for the implementation of the QVCO include parallel-coupled (P-QVCO) [20], [21], series-coupled [22], in-phase injection-coupled (IPIC-QVCO) [23], magnetically-coupled resonator [24] and superharmonic-coupled (SH-QVCO) [25]. The coupling method chosen for the QVCO (Fig.…”

Section: A Coupling Methodsmentioning

confidence: 99%

“…The main disadvantage of the SH-QVCO is weak coupling, which might lead to an excessive I/Q phase error as mentioned in [23]. This is especially true at millimeter wave: the 120 GHz transformer at the core of has a coupling factor of around 0.5, but extra routing inductance diminishes the transformer's effect in selecting the desired mode.…”

Section: A Coupling Methodsmentioning

confidence: 99%

See 2 more Smart Citations

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Szortyka

Shi

Raczkowski

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

A 60 GHz sub-sampling PLL implemented in 40 nm CMOS is presented in this paper. The sub-sampling phase detector (SSPD) runs at 30 GHz after an inductively-peaked static divideby-two. Thanks to the lower frequency of operation, the effect of non-zero sampling aperture of the switch is minimized. A dummy divider of the quadrature PLL is utilized for the sub-sampling loop to avoid extra loading in the 60 GHz path. A 53.8-63.3 GHz QVCO uses super-harmonic coupling at 120 GHz for relaxed headroom at a 0.9 V supply and achieves a free-running phase noise down to 94.5 dBc/Hz at 1 MHz offset. The millimeter-wave sub-sampling PLL achieves an RMS jitter, integrated from 1 kHz to 100 MHz, of 200 fs at a power consumption of 42 mW, compared to 210 fs for the PFD/CP PLL at 75 mW. Reference spurs in both modes are below 40 dBc. Index Terms-CMOS, frequency synthesizer, millimeter-wave, oscillators, PLL, quadrature voltage-controlled oscillator(QVCO). 0018-9200

show abstract

Section: Resultsmentioning

confidence: 99%

Section: A Coupling Methodsmentioning

confidence: 99%

Section: A Coupling Methodsmentioning

confidence: 99%

See 1 more Smart Citation

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Szortyka

Shi

Raczkowski

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…Reference [5] reported a ring-based transformer-coupled 60-GHz QVCO with a PN performance of −117 dBc/Hz at 10-MHz offset. A diode-connected-transistor coupled 60-GHz QVCO in [6] reached low power and a PN of −115 dBc/Hz at 10-MHz offset.…”

Section: Introductionmentioning

confidence: 99%

Low-Phase-Noise 54-GHz Transformer-Coupled Quadrature VCO and 76-/90-GHz VCOs in 65-nm CMOS

Guo

Gui

et al. 2016

IEEE Trans. Microwave Theory Techn.

View full text Add to dashboard Cite

This paper presents new circuit topologies and design techniques for low-phase-noise (PN) complementary metal-oxide-semiconductor (CMOS) millimeter-wave quadrature voltage-controlled oscillator (QVCO) and VCOs. A transformer-coupled QVCO topology with extra phase shift is proposed to replace the coupling transistors, which eliminates coupling transistors' noise, decouples the tradeoff between PN and phase error, and improves the PN performance. This technique is demonstrated in a millimeter-wave QVCO with a measured PN of −119.2 dBc/Hz at 10-MHz offset of a 56.2-GHz carrier and a tuning range of 9.1%. In addition, an inductivedivider-feedback technique is proposed in an LC VCO design to improve the transconductance linearity, resulting in a larger signal swing and lower PN compared with the conventional LC VCOs. The effectiveness of this approach is demonstrated in a 76-and a 90-GHz VCO design, both fabricated in a 65-nm CMOS process, with an FOM T of 173.6 and 173.1 dBc/Hz, respectively. Index Terms-Oscillator, phase error, phase noise (PN), quadrature voltage-controlled oscillator (QVCO), transconductance linearization, transformer, VCO. 0018-9480

show abstract

“…In fact, OOK with the envelope detection in the receiver can be implemented without the LO requiring a PLL in either the receiver or transmitter. Since LO generation consumes significant portion of the total power, its elimination significantly reduces the power consumption [18], [19]. A 1 1 OOK transceiver with on-chip antennas is reported in [20] where it uses return-to-zero (RZ) signaling with pulse-width control (PWC) to reduce the power consumption.…”

Section: Introductionmentioning

confidence: 99%

An Energy Harvesting 2$\times$2 60 GHz Transceiver With Scalable Data Rate of 38–2450 Mb/s for Near-Range Communication

Taghivand¹,

Aggarwal

Rajavi

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

A fully integrated 2 2 CMOS transceiver at 60 GHz with energy harvesting capability in the transmitter mode and on-chip dipole antennas is demonstrated. The radio supports on-off-keying (OOK) modulation and a programmable data rate of 38 to 2450 Mb/s at a BER of less than 5 10 . The power consumption of the transmitter scales with data rate from 100 W to 6.3 mW at 5 cm range and from 260 W to 11.9 mW at 10 cm range. This yields an energy efficiency of 2.6 pJ/b at 5 cm and 4.9 pJ/b at 10cm. The energy harvesting circuits operate at 2.45 GHz with an average efficiency of 33%. The harvesting antenna and its matching components are off-chip. The complete transceiver including the energy harvesting block and on-chip antennas occupies 1.62 mm in 40 nm CMOS.Index Terms-Close range, dipole antenna, energy harvest, impulse radio, IR-UWB, low power, MIMO, mmWave, near range, on-chip antenna, OOK, power harvest, 60 GHz, 2 2, ultra wide band.

show abstract

A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology

Cited by 100 publications

References 23 publications

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS

Low-Phase-Noise 54-GHz Transformer-Coupled Quadrature VCO and 76-/90-GHz VCOs in 65-nm CMOS

An Energy Harvesting 2$\times$2 60 GHz Transceiver With Scalable Data Rate of 38–2450 Mb/s for Near-Range Communication

Contact Info

Product

Resources

About