A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition

Oh, Jinwook; Kim, Gyeonghoon; Nam, Byeong-Gyu; Yoo, Hoi‐Jun

doi:10.1109/jssc.2013.2280238

Cited by 14 publications

(12 citation statements)

References 22 publications

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“…In most cases, digital or other analog circuits are attached around a partially tunable Gaussian or Gaussian-like function circuit (Figure 28) to improve the tunability of the Gaussian function curve's three characteristics (height, mean value and variance). The extra components include multiplexers (MUX) [11,81] and/or switches [15,[82][83][84][85] and other digital circuitry (mixed-mode architectures [86]) [82][83][84], series of resistors [19,87,88], DACs [22,28,87] or Analog to Digital converters (ADC) [22], multipliers [28,31,33,87] or tunable current mirrors [89,90], OTAs [91][92][93][94] or other amplifiers [12,87], common mode feedback circuits (CMFB) [22,95], squarers [33], exponentiators [87], current-controlled current-conveyor second generation (CCII) circuits [90], minimum value circuits [96] and additional current correlators [97]. Four representative examples are provided in Figures 29-32.…”

Section: Designs Incorporating Extra Componentsmentioning

confidence: 99%

“…In a similar manner, the series of resistors alter the Gaussian function output by changing the total resistance value [19,87,88]. Moreover, DACs, multipliers, squarers or tunable current mirrors usually directly affect the height of the Gaussian function [22,28,31,33,87,89,90]. There are implementations that use OTAs as current to voltage converters [91] or deploy three OTAs along with multiple resistors as basic building blocks to design tunable Gaussian function circuits [92][93][94].…”

Section: R Tunementioning

confidence: 99%

“…Since the first Gaussian function circuit (also called the Bump circuit) was introduced by Delbruck (Delbruck's Simple Bump) in 1991 [1,2] (shown in Figure 1), many research groups have focused on improving this architecture and/or incorporating it in various fields [3][4][5][6][7][8][9][10][11][12][13][14]. Some of the implementations are used for Machine Learning (ML) applications [15,16], neuromorphic systems [17,18], smart sensors [19,20] and fuzzy or neuro-fuzzy systems [21,22]. Gaussian function circuits are specific analog circuits that provide an output current, which is a typical Gaussian function [23] or a bell-shaped curve [24].…”

Section: Introductionmentioning

confidence: 99%

“…We note that a primary aim in the design flow of most Gaussian function circuits is the independent and electronic tunability of the Gaussian curve's characteristics (height, mean value and variance) [27][28][29]. By designing a fullytunable architecture, the Gaussian function circuit can be used as a general purpose circuit in multiple applications [22]. On the other hand, a design lacking electronic tunability is focused on a specific application [9].…”

Section: Introductionmentioning

confidence: 99%

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Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

et al. 2021

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This review paper explores existing architectures, operating principles, performance metrics and applications of analog Gaussian function circuits. Architectures based on the translinear principle, the bulk-controlled approach, the floating gate approach, the use of multiple differential pairs, compositions of different fundamental blocks and others are considered. Applications involving analog implementations of Machine Learning algorithms, neuromorphic circuits, smart sensor systems and fuzzy/neuro-fuzzy systems are discussed, focusing on the role of the Gaussian function circuit. Finally, a general discussion and concluding remarks are provided.

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Section: Designs Incorporating Extra Componentsmentioning

confidence: 99%

Section: R Tunementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

et al. 2021

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“…A SIFT object recognition processor in [20] was proposed with a top-down visual attention feedback loop implementing neural-fuzzy inference to improve visual attention. The latest neural-fuzzy object recognition processor in [21] was designed to perform inference and learning using neural-fuzzy algorithms. Impressive performance and energy efficiency have been reported.…”

mentioning

confidence: 99%

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Knag

Kim

Chen

et al. 2015

IEEE J. Solid-State Circuits

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Hardware-based computer vision accelerators will be an essential part of future mobile devices to meet the low power and real-time processing requirement. To realize a high energy efficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to vision processing, which is an advantage over software-based solutions and general-purpose hardware. In this work, we present an ASIC that is designed to learn and extract features from images and videos. The ASIC contains 256 leaky integrate-and-fire neurons connected in a scalable two-layer network of 8 8 grids linked in a 4-stage ring. Sparse neuron activation and the relatively small grid keep the spike collision probability low to save access arbitration. The weight memory is divided into core memory and auxiliary memory, such that the auxiliary memory is only powered on for learning to save inference power. High-throughput inference is accomplished by the parallel operation of neurons. Efficient learning is implemented by passing parameter update messages, which is further simplified by an approximation technique. A 3.06 mm 65 nm CMOS ASIC test chip is designed to achieve a maximum inference throughput of 1.24Gpixel/s at 1.0 V and 310 MHz, and on-chip learning can be completed in seconds. To improve the power consumption and energy efficiency, core memory supply voltage can be reduced to 440 mV to take advantage of the error resilience of the algorithm, reducing the inference power to 6.67 mW for a 140 Mpixel/s throughput at 35 MHz.Index Terms-Feature extraction, hardware acceleration, neural network architecture, sparse coding, sparse and independent local network.

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Recent development in analog computation: a brief overview

Xue

2015

Analog Integr Circ Sig Process

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-The recent development in analog computation is reviewed in this paper. Analog computation was used in many applications where power and energy efficiency is of paramount importance. It is shown that by using innovative architecture and circuit design, analog computation systems can achieve much higher energy efficiency than their digital counterparts, as they are able to exploit the computational power inherent to the devices and physics.However, these systems do suffer from some disadvantages, such as lower accuracy and speed, and designers have come up with novel approaches to overcome them. The paper provides an overview of analog computation systems, from basic components such as memory and arithmetic elements, to architecture and system design.

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A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition

Cited by 14 publications

References 22 publications

Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

Analog Gaussian Function Circuit: Architectures, Operating Principles and Applications

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Recent development in analog computation: a brief overview

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