A 57-to-66GHz quadrature PLL in 45nm digital CMOS

Scheir, Karen; Vandersteen, Gerd; Rolain, Yves; Wambacq, Piet

doi:10.1109/isscc.2009.4977524

Cited by 79 publications

(34 citation statements)

References 3 publications

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“…This range covers operation over 22. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26]. 4 GHz, with margin, meeting requirements for a 60-GHz superheterodyne radio [2].…”

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confidence: 99%

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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Abstract-This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 temperature variation is 3 dB. At the 25 GHz center frequency, the VCO is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

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confidence: 99%

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing

Sadhu

Ferriss

Natarajan

et al. 2013

IEEE J. Solid-State Circuits

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“…Fig. 2 shows the three main approaches to designing a 60 GHz LO system that generates quadrature outputs starting with using a PLL with a QVCO running directly at the fundamental frequency [9]. A second approach uses a PLL with a differential [10], [11] or a push-push VCO [12]- [14] followed by a polyphase filter or a hybrid coupler [15] to generate I/Q signals.…”

Section: Ghz Lo Topologiesmentioning

confidence: 99%

“…This complicates the design process and increases the number of design iterations needed. Some have used multiple QVCOs to reduce the effect of both these drawbacks [9], however this approach did not improve the phase noise much since the obtained phase noise at dBc/Hz@1 MHz was still about 15 dB less than the required phase noise for 16QAM. Finally, designing a frequency divider to operate at this high frequency would be difficult in terms of locking range and area for those utilizing inductors and would consume high power for an inductorless one [11].…”

Section: A 60 Ghz Qvcomentioning

confidence: 99%

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

Musa

Murakami

Sato

et al. 2011

IEEE J. Solid-State Circuits

115

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This paper proposes a 60 GHz quadrature PLL frequency synthesizer for the IEEE802.15.3c with wide tuning range and low phase noise. The synthesizer is constructed using a 20 GHz PLL that is coupled with a Quadrature Injection Locked Oscillator (QILO) as a frequency tripler to generate the 60 GHz signal. The 20 GHz PLL generates a signal with a phase noise that is lower than dBc/Hz using tail feedback to improve the phase noise while having a 17% tuning range. The proposed 60 GHz QILO uses a combination of parallel and tail injection to enhance the locking range by improving the QILO injection efficiency at the moment of injection and has a 12% tuning range. Both the 20 GHz PLL and the QILO were fabricated as separate chips using a 65 nm CMOS process and measurement results show a phase noise that is less than 95 dBc/Hz@1 MHz at 60 GHz while consuming 80 mW from a 1.2 V supply. To the author's knowledge this phase noise is about 20 dB better than recently reported QPLLs and about 10 dB compared to differential PLLs operating at a similar frequency and at a similar offset.

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“…The 7 GHz of contiguous bandwidth available at 60 GHz, though very useful, poses circuit design challenges especially for components like VCOs, prescalers and PLLs in a direct conversion transceiver [4][5][6][7]. Therefore, alternative synthesizer friendly architectures based on double-heterodyne, sliding-IF, low-IF and half-RF architectures are being investigated [1][2][3].…”

Section: Introductionmentioning

confidence: 99%