A 5V-only E<sup>2</sup> PROM using 1.5 µ lithography

Dham, V.K.; Oto, D.; Gudger, K.; Congwer, G.; Hu, Y.W.; Olund, J.; Nieh, S. T. K.

doi:10.1109/isscc.1983.1156502

Cited by 2 publications

(1 citation statement)

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“…Fig. 2 illustrates a conventional nMOS switch composed of only high-voltage nMOSFETs used in flash memories [10], [11]. Unlike CMOS switches with large parasitic capacitance of n-well for pMOSFETs, this nMOS-only switch has small gate, junction, and wiring capacitance, resulting in low power consumption and short charging time.…”

Section: Introductionmentioning

confidence: 99%

Circuit techniques for a 1.8-V-only NAND flash memory

Tanzawa

Tanaka

Takeuchi

et al. 2002

IEEE J. Solid-State Circuits

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Abstract-Focusing on internal high-voltage () switching and generation for low-voltage NAND flash memories, this paper describes a switch, row decoder, and charge-pump circuit. The proposed nMOS switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 A. The proposed pump scheme reduced the area required for charge-pump circuits by 40%.Index Terms-Charge-pump circuit, high-voltage switching, low supply voltage, NAND flash memories, row decoder.

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Section: Introductionmentioning

confidence: 99%