A 6.05-Mb/mm²16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time

Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing

“…This technique consists in artificially duplicating the number of ports by generating a second internal memory clock to start a consecutive memory access without waiting for the end of the first clock. This is made possible by modifiying decoding and IO circuitry in order to add intermediate sequences of dynamic logic, while reducing the operating frequency (up to ~40%) [11][12][13][14][15]. Nowadays, most of founders and IP vendors propose 2-Port SRAM compilers based on SP bitcells that use this technique to improve both memory density and leakage power consumption at the expense of operating frequency compared to the reference solution (Fig.…”

“…Table 1 describes the different configurations (memory size, maximum operating frequency …) of the C-SRAM macros selected for this study. Note that he results obtained in this section for 2RW-DP and 4RW-DP C-SRAM configurations have been extrapolated from simulation of 1RW and 2RW C-SRAM configurations based on [11][12][13][14][15][16]. The maximum operating frequency varies between 1.5GHz to 2.2GHz for 4RW-DP and 2RW cuts of 128-word (minimum size) of 128bit, respectively.…”

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

“…However, the inverter incurs a full-swing signal when "1" is read out. A small-signal sensing scheme using a differential sense amplifier is often adopted [21,23,24], which consequently achieves much higher operating frequency. However, such circuitry requires dedicated signal timing and a greater area cost.…”

“…The differential voltage between a read bitline (RBL) of the selected MAT and that of an unselected MAT is amplified in readout operation at higher frequency. Reportedly [24], a 1R1W dual-port SRAM in a 16-nm Fin-FET technology was achieved by 6T single-port SRAM bitcells with double-pumping internal clock for high speed and high density. The double-pumping clock scheme for an internal clock generator achieves robust timing design without strict severe setup/hold margins, and achieves lower operating voltage of 680 mV using a negative-level write driver.…”

“…The double-pumping clock scheme for an internal clock generator achieves robust timing design without strict severe setup/hold margins, and achieves lower operating voltage of 680 mV using a negative-level write driver. Nevertheless, these devices and methods all require dedicated signal timing and entail a greater area cost [21,23,24].…”