Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector Processing

Abstract

This paper presents a new methodology for automating the Computational SRAM (C-SRAM) design based on off-the-shelf memory compilers and a configurable RTL IP. The main goal is to drastically reduce the development effort compared to a full-custom design, while offering a flexibility of use and a high-yield production. The proposed C-SRAM architecture has been developed to process energy-efficient vector data coupled with a scalar processor, while limiting the data transfer on the system bus. The results obtained by post P&R simulations show that 2RW and 4RW C-SRAM configurations using the double pumping technique achieved the highest performance to process vectorized MAC operations compared to the others configurations. Moreover, it has been shown that the impact of the digital wrapper decoding and executing the instructions can be mitigated by increasing the memory cut size to represent less than 10% in area and 20% in power consumption.

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator

“…ALU operations can be parametered to perform parallel computation on 8-bit to 32-bit operations. Previous works [2], [14], [15] provided details regarding the specification, the design and the characterization of this architecture, and additional works [9], [16] investigated C-SRAM integration in elaborate scenarios. In this paper, our experimental C-SRAM architecture is a 128-bit single unit supporting 16 × 8 up to 32 × 4 vector operations.…”

Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization

“…The C-SRAM architecture 67.20 * * SRAM memory access in one instruction. Notes: RISC-V numbers are adapted from [5] in GF 22nm, C-SRAM numbers are from Place&Route results under GF 22nm in [17] and SIMD instruction numbers are adapted according to the bus width as explained in Section 5.2.…”

“…integrates both IMC operations (bitwise logic) and NMC operations (ADD, MULT ). It has been designed in a GF 22nm FDSOI technology and implemented with different floor-plans configurations up to final Place&Route [17]. We have selected a 4 kB SRAM configuration: the C-SRAM single tile performance numbers (timing and energy access) are extracted for the multi-tile architecture exploration.…”

“…In order to evaluate this architecture, we propose an instruction accurate simulation platform that considers all transaction events between hardware components and its integration into a standard software tool chain. For accurate architecture exploration, all low level performance numbers (cycles and energies) are extracted from Place&Route implementation in 22nm FDSOI technology, as presented in [17]. Using the simulation platform, we evaluate the performance speed up, the energy reduction and the Energy Delay Product (EDP) reduction of the reconfigurable vector-based C-SRAM tiles architecture compared to tightly-coupled 128-bit, 256-bit and 512-bit SIMD architectures, using the same vectorized kernels.…”

Storage Class Memory with Computing Row Buffer: A Design Space Exploration

“…Having a close look at the SCM architecture, one can notice that the communication between the SCM and the rest of the hierarchy is performed through a volatile Row-Buffer (RB) [10]. Our key idea is to replace the RB of the SCM by a Computing-RB (C-RB), following a C-SRAM architecture [11], to achieve significant energy reduction and speedup. By doing so, we get the best of both worlds: high data density from SCM and fast and low energy accesses from SRAM.…”