Reconfigurable tiles of computing-in-memory SRAM architecture for scalable vectorization

Abstract

For big data applications, bringing computation to the memory is expected to reduce drastically data transfers, which can be done using recent concepts of Computing-In-Memory (CIM). To address kernels with larger memory data sets, we propose a reconfigurable tilebased architecture composed of Computational-SRAM (C-SRAM) tiles, each enabling arithmetic and logic operations within the memory. The proposed horizontal scalability and vertical data communication are combined to select the optimal vector width for maximum performance. These schemes allow to use vector-based kernels available on existing SIMD engines onto the targeted CIM architecture. For architecture exploration, we propose an instruction-accurate simulation platform using SystemC/TLM to quantify performance and energy of various kernels. For detailed performance evaluation, the platform is calibrated with data extracted from the Place&Route C-SRAM circuit, designed in 22nm FDSOI technology. Compared to 512-bit SIMD architecture, the proposed CIM architecture achieves an EDP reduction up to 60× and 34× for memory bound kernels and for compute bound kernels, respectively.

Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM

“…In this paper, we focus on an SRAM-based bit-parallel architecture, which shows a better compromise between computation capability, system integration and data compatibility [2][3][4].…”

“…We propose a data-locality management unit (DMU), a transfer block presented in Figure 1b, coupled to an SRAM-based IMC unit to generate efficient data transfer and reorganization through a dedicated instruction set. As IMC architecture, we consider the computational SRAM (C-SRAM), an SRAM-based bit-parallel IMC architecture detailed in [2][3][4], and able to perform logical and arithmetical operations in-parallel thanks to an arithmetic and logic unit (ALU) in its periphery. We integrate it within a CPU and a DRAM as main memory.…”

Storage Class Memory with Computing Row Buffer: A Design Space Exploration

“…The IMC SRAM circuit proposed in [3], allowing logic operations and addition, reaches up to 6× speedup compared to a NEON CPU. Reconfigurable architecture using SRAM memories is considered in [13] to meet various requirements either from the application or from the data pattern used during different application phases. The programming model of this reconfigurable architecture is compatible with SIMD programming and show a 60× EDP reduction compared to a SIMD 512 bits architecture.…”

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator

“…This is a very fast method of prototyping in terms of development effort and simulation speed, but it shows low fidelity to a physical implementation. Other solutions such as [3] [4] [5] use elaborate frameworks such as SystemC or gem5 to perform cycle-accurate system modeling. These frameworks show very high fidelity to physical implementations but low simulation speed due to their complexity.…”