Storage Class Memory with Computing Row Buffer: A Design Space Exploration

Abstract

Today computing centric von Neumann architectures face strong limitations in the data-intensive context of numerous applications, such as deep learning. One of these limitations corresponds to the well known von Neumann bottleneck. To overcome this bottleneck, the concepts of In-Memory Computing (IMC) and Near-Memory Computing (NMC) have been proposed. IMC solutions based on volatile memories, such as SRAM and DRAM, with nearly infinite endurance, solve only partially the data transfer problem from the Storage Class Memory (SCM). Computing in SCM is extremely limited by the intrinsic poor endurance of the Non-Volatile Memory (NVM) technologies.In this paper, we propose to take the best of both solutions, by introducing a Computing Row Buffer (C-RB), using a Computing SRAM (C-SRAM) model, in place of the standard Row Buffer (RB) in the SCM. The principle is to keep operations on large vectors in the C-RB of the SCM, minimizing data movement to and from the CPU, thus drastically reducing energy consumption of the overall system. To evaluate the proposed architecture, we use an instruction accurate platform based on Intel Pin software. Pin instruments run time binaries in order to get applications' full memory traces of our solution. We achieve energy reduction up to 7.9x on average and up to 45x for the best case and speedup up to 3.8x on average and up to 13x for the best case, and a reduction of write accesses in the SCM up to 18%, compared to SIMD 512-bit architecture.

Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems

“…It must be large enough to support a certain algorithmic complexity (e.g. by storing data that will be used several times), and therefore cannot be limited to a bank of registers [3,4,7]. -DMU: It is responsible for managing the data between FeRAM and C-SRAM.…”

“…A critical question then arises: How can resource-constrained MCUs rise to the challenge without compromising the predictability, reliability and safety of critical embedded systems (CES)? This is where the Compute-In-Place (CIP) method exploited in a Serial Ferroelectric RAM (FeRAM) architecture, leveraging the Computational SRAM (C-SRAM) concept [3][4][5][6][7][8][9][10], becomes pivotal. This paper explores the novel integration of the CIP method within Serial FeRAM and its reliance on C-SRAM.…”

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator

“…ALU operations can be parametered to perform parallel computation on 8-bit to 32-bit operations. Previous works [2], [14], [15] provided details regarding the specification, the design and the characterization of this architecture, and additional works [9], [16] investigated C-SRAM integration in elaborate scenarios. In this paper, our experimental C-SRAM architecture is a 128-bit single unit supporting 16 × 8 up to 32 × 4 vector operations.…”