Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units

Abstract

In-Memory Computing (IMC) aims at solving the performance gap between CPU and memories introduced by the memory wall. However, general-purpose IMC does not consider the optimization of data transfers for patterns such as stencils and convolutions. This paper proposes a new Instruction Set Architecture (ISA) and a novel pattern encoding for IMC to transfer and organize data streams in order to perform efficiently computation. This instruction set is implemented on the Data-locality Management Unit (DMU) as a subset of the Computational SRAM (C-SRAM) Instruction Set Architecture. A programming model to interact with the DMU at languagelevel is also presented in this paper. This DMU ISA is evaluated on six applications run on three different system nodes. These system nodes are based on existing RISC-V cores and range from embedded to high-performance computing domain. Experiments show on average a speed-up of ×8.81, an energy reduction factor of ×6.81 and an improvement of the number of operations per cycle of ×4.59, for The C-SRAM architecture integrating the proposed ISA of the DMU compared to a reference implementation on embedded systems. Results also show an improvement of the number of operations per cycle of ×2.99 compared to a reference implementation on all system nodes.

Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical Embedded Systems

“…-DMU: It is responsible for managing the data between FeRAM and C-SRAM. It performs operations such as format conversion, data compression and normalization to ensure that data is ready for processing by the vector processor unit [10]. -Controller: It coordinates all operations between FeRAM, DMU, C-SRAM and MCU.…”

“…A critical question then arises: How can resource-constrained MCUs rise to the challenge without compromising the predictability, reliability and safety of critical embedded systems (CES)? This is where the Compute-In-Place (CIP) method exploited in a Serial Ferroelectric RAM (FeRAM) architecture, leveraging the Computational SRAM (C-SRAM) concept [3][4][5][6][7][8][9][10], becomes pivotal. This paper explores the novel integration of the CIP method within Serial FeRAM and its reliance on C-SRAM.…”