A 6.3-ppm/°C, 100-nA Current Reference With Active Trimming in 28-nm Bulk CMOS Technology

Abstract

This paper introduces a current reference based on ∆V GS generation principle and adopts integrated poly-p+ resistors and a nW-power OTA to reduce the line sensitivity. Implemented in a 28-nm standard CMOS technology, the circuit provides a nominal current equal to 100nA and operates down to 0.6 V with a line sensitivity equal to 1.2 %/V in the range [0.8-1.8] V and a temperature coefficient equal to 6.3 ppm/°C in the range [10-90]°C. Comparison with the state-of-the-art confirms the validity of the proposed solution and its suitability to be exploited in ultra-low-power and area-constrained applications.INDEX TERMS Current reference, low voltage, low power, area-efficient, Internet of Things, sensor nodes, implanted biomedical devices NOMENCLATURE

A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI

“…This leads to a non-zero I DS2 which starts the reference. Other CWT PCRs employing slightly different ideas exist in the literature, such as [16], [17], biasing the resistor with the ∆V T between transistors of the same V T type but different lengths, and [18], making use of an additional degeneration resistor to achieve temperature compensation. Yet, these works are either limited to simulations and/or generate a larger I REF .…”