A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Yu, Changzhi; Sa, Euije; Jin, Soowan; Park, Himchan; Shin, Jongshin; Burm, Jinwook

doi:10.1109/jssc.2020.3005750

Cited by 28 publications

(2 citation statements)

References 15 publications

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“…The state-of-the-art CDRs use a separate frequency detector (FD) [7][8][9][10][11][12][13] and dual-loop structure [14][15][16][17][18][19] to extend the capture range, thus increasing the design complexity and hardware cost. Another evolution has opted for an analog-to-digital converter (ADC)-based scheme and a great amount of signal processing in the digital domain, [20][21][22][23][24] which leads to large power consumption and loop latency. Even if some solutions have been proposed in previous studies, [25][26][27][28][29][30][31] they either require complex loop topologies 25,31 and large power consumption [26][27][28] or result in a limited capture range.…”

Section: Introductionmentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

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This paper reports a bang-bang clock and data recovery circuit (BBCDR) with an ultra-wide capture range. The circuit exhibits automatic frequency capture and phase locking over a wide 6-to-38 Gb/s range without using a frequency detector, allowed by a recently proposed deliberate-current-mismatch technique. Moreover, we accurately obtain an eight-phase clock through analog interpolation of quadrature signals over the whole wide frequency range by introducing a tunable capacitor array before an inverter-based phase interpolator. A 65-nm prototype of the developed BBCDR occupies an area of 0.07 mm 2 and attains a bit error rate of less than 10 À12 under a continuously variable input frequency, with a total power consumption of 24.6 mW for a 32-Gb/s non-return-zero input, thus leading to 0.769-pJ/bit energy efficiency.bang-bang clock and data recovery (BBCDR), current mismatch, frequency detector (FD), hybrid control circuit (HCC), phase interpolator (PI), ring oscillator (RO), R-2R digital-toanalog converter (DAC), switched-capacitor (SC) array, wide capture range

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Section: Introductionmentioning

confidence: 99%

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

Wang

Chen

Yang

et al. 2023

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…However, the single-loop structure without frequency detector (FD) has a narrow frequency capture range so that it can only be used in a narrow range of data rates. Reference [21] proposes a 6.5-12.5 Gb/s half-rate single-loop all-digital reference-less CDR. A novel frequency tracking method based on the extended bang-bang phase detector (XBBPD) is used to broaden the frequency locking range and shorten the locking time to 1500 ns.…”

Section: Introductionmentioning

confidence: 99%

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

Pan

Shi

Zhao

et al. 2022

IEICE Electron. Express

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This paper presents a 21.3-24.5 Gb/s phase locked loop (PLL)-based reference-less clock and data recovery (CDR) circuit. A cascode-coupled technique is used in the design of the quadrature voltagecontrolled oscillator (VCO), which eliminates the phenomenon of dualmode oscillation, provides a stable phase sequence for frequency acquisition and ensures the correct loop locking. The dual loop topology is adopted to realize a wide frequency acquisition range and an autonomous transition from frequency locking to phase locking, while the PLL-based structure brings in an excellent jitter performance. When the data rate of the input PRBS9 is 24.5 Gb/s, the measured peak-to-peak jitter and the rootmean-square (RMS) jitter of the recovered clock are 2.7 ps and 0.39 ps respectively, and the peak-to-peak jitter and the RMS jitter of the recovered data are 7.7 ps and 1.5 ps respectively. Implemented in 55-nm CMOS technology, the CDR circuit occupies a core area of 0.7mm 2 and consumes 170mW at 1.2V power supply.

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A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

Chen

Fan

et al. 2023

Circuits Syst Signal Process

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A 6.5–12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS

Cited by 28 publications

References 15 publications

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

A 6‐to‐38Gb/s capture‐range bang‐bang clock and data recovery circuit with deliberate‐current‐mismatch frequency detection and interpolation‐based multiphase clock generation

A 21.3-24.5Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

A 2–20 Gbps Clock and Data Recovery Based on Phase Interpolation and Delay Locked Loop

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