A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Bichan, Mike; Carusone, Anthony Chan

doi:10.1109/cicc.2008.4672161

Cited by 21 publications

(15 citation statements)

References 5 publications

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“…These values are consistent when comparing to literature with similar systems and data rates [1], [2]. The receiver on the other hand, being fully functional except for the low quality pulses generated, dissipates 19.8 mW compared to the simulated value of 18 mW.…”

Section: Resultssupporting

confidence: 79%

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

Goosen

Sinha

2011

Microelectronics Journal

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Due to advances of technology in multimedia applications in recent years, the demand for high user end bandwidth point to point links has increased significantly. Jitter requirements have become ever more stringent with the increase in high speed serial link data rates. The introduced jitter severely degrades the performance of the high speed serial link. This paper introduces an adaptive FIR pre-emphasis technique as a means to alleviate the problem of limited off-chip bandwidth introducing data dependant jitter. Mathematical as well as SPICE simulation results are presented, together with the implemented integrated circuit layouts of the novel 0.18 μm CMOS implementation. Limited results from the experimentally tested IC are also presented and discussed. The adaptive pre-emphasis technique employed results in a simulated data dependant jitter reduction to less than 12.5 % of a unit interval at a data rate of 5 Gb/s and a modelled 30" FR-4 backplane copper channel.

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Section: Resultssupporting

confidence: 79%

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

Goosen

Sinha

2011

Microelectronics Journal

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“…In fact, this equalizer yields almost a constant slope at transition edges, which makes it more resistible to jitter. Compared with the equalizer shown in Fig.4(a) which has a representative implementation in [7], this equalizer gives an eyediagram with a thinner "eyelid" and it has a larger horizontal and vertical eye opening.…”

Section: Simulation Resultsmentioning

confidence: 99%

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously

Chen

Wang

Liang

et al. 2009

2009 Canadian Conference on Electrical and Computer Engineering

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This paper presents a 10-Gb/s backplane transmitter with a finite impulse response (FIR) pre-emphasis equalizer to suppress inter-symbol-interference (ISI) at data centers and transition edges simultaneously. The design concepts are discussed. Circuits in 0.13µm IBM CMOS technologies are given. Comparison with conventional data center oriented equalizer and transition edge oriented equalizer are carried out on a 40-inch FR4 differential backplane.

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“…It can be verified that (10) so that the modulo-2L reduction of w n depends only on the digit a n . Based on the relation (10), symbol-by-symbol detection can be performed on [z n ] 2L .…”

Section: Error Performance Analysismentioning

confidence: 99%

“…In [4], a 2-tap pre-equalizer with fractional delay is optimized numerically to minimize a semi-analytically computed bit error rate (BER). In [10], the coefficients of a 6-tap equalizer are represented by 4 bits, and their values are optimized by means of a numerical search to mimimize data-dependent jitter. In [9], a combination of an FIR pre-equalizer and a one-tap DFE is considered for partial response signaling; a minimum mean-square error (MMSE) criterion is used to determine the filter taps.…”

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confidence: 99%

Performance analysis of pre-equalized multilevel partial response schemes

Guenach

Jacobs

Kozicki

et al. 2015

2015 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)

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Abstract-In order to achieve high speed on electrical interconnects, channel attenuation at high frequencies must be dealt with by proper transceiver design. In this paper we investigate finitecomplexity MMSE pre-equalization under an average transmit power constraint, to compensate for channel distortion in the case of both full-response and precoded partial response signaling with L-PAM mapping, and consider the resulting error performance for symbol-by-symbol detection and sequence detection. For a representative electrical interconnect, we point out that the constellation size (2-PAM or 4-PAM), the type of signaling (full response or partial response), the detection method (symbol-bysymbol detection or sequence detection) and the number of preequalizer taps should be carefully selected in order to achieve satisfactory error performance at high data rates. For several scenarios, precoded duobinary 4-PAM is found to yield the best error performance for given average transmit power.

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A 6.5 Gb/s backplane transmitter with 6-tap FIR equalizer and variable tap spacing

Cited by 21 publications

References 5 publications

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

Reducing data dependent jitter utilising adaptive FIR pre-emphasis in 0.18 μm CMOS

A 10-Gb/s backplane transmitter with a FIR pre-emphasis equalizer to suppress ISI at data centers and edges simultaneously

Performance analysis of pre-equalized multilevel partial response schemes

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