A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS

Abstract

Digital receivers for high bit-rate communications are spurring on the required conversion rate of A/D converters. State-of-theart disk drive read channels and high-speed Ethernet signals use partial response signaling, requiring 6b resolution at conversion rates of 1GHz and beyond, and an effective resolution bandwidth of half the Nyquist frequency. Furthermore, continuous DVD playback and certain Ethernet uses permit no idle times when the linearity of the A/D converter may be self-calibrated by autozeroing. This work reports on a 6b ADC without autozero or selfcalibration, which digitizes a 630MHz input with a linearity of 5.5 effective bits at 1GSample/s, and a 650MHz input with 5 effective bits at 1.3GSample/s. At conversion rates of 1GSample/s and beyond, the only practical architecture to date is the flash ADC. As MOSFETs in the preamplifiers are sized up to lower random mismatch to resolve a typical full-scale of 1.6V to 6b, the power consumption and input capacitance also grow to a point that the ADC may no longer be readily embedded in a receiver chip. This ADC uses resistor averaging in two places to filter out random mismatch between arrays of differential pairs, substantially improving the accuracy of small MOSFETs which bias at a small current and present low input capacitance. Previous work [1] presents a systematic method to design averaging networks based on spatial filtering. With the proper number of dummy preamplifiers at each end of the array, the optimum averaging network lowers INL by 3.3x. To obtain the same linearity without averaging, FET W/L, and therefore power dissipation, must be scaled by 10x.

Adaptive quantization using piecewise companding and scaling for Gaussian mixture

“…The number of quantization levels could be adjusted according to the speed, resolution and power consumption of the devices. Our scheme based on histogram estimation and the GMM modeling may outstand previous iterative DPCM schemes [13].…”

A 6b 1.2 GS/s 47.8 mW 0.17 mm265 nm CMOS ADC for High-Rate WPAN Systems

“…Of various T/H architectures, the T/H composed of sampling capacitors, sampling and dummy switches, and source followers has been commonly employed. In the conventional T/H, the switch and clock feed-through errors during the mode transition from sampling to holding and the signal distortion caused by the source followers degrade the overall ADC linearity [10]. Particularly, the source followers show a critical signal distortion with an increasing input signal range and dissipate more power with an increasing sampling rate.…”

“…The DDA as illustrated in Fig. 4 has been used as the first-stage pre-amp of a highspeed comparator since it operates at high speed without the glitch noise and gain reduction due to sampling switches and capacitors [10,12]. At the output of the DDA, passive resistors or diode-connected MOS transistors are usually employed to obtain the required DC gain and bias voltage.…”

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

“…Typically, six-bit resolution with a sampling rate of several hundred megahertz is required. Even gigahertz rates seem to be within the reach of state-of-the-art CMOS technologies [48,49].…”