A 6 b 800 MSample/s CMOS A/D converter

Sushihara, K.; Kimura, Hiroshi; Okamoto, Yuki; Nishimura, K.; Matsuzawa, Akira

doi:10.1109/isscc.2000.839845

Cited by 16 publications

(9 citation statements)

References 3 publications

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“…These currents are mirrored from load transistors (Mp1 and Mp2) to p-channel transistors (Mp3 and Mp4). A pair of p-channel cascode transistors (Mp5 and Mp6) biased at a given voltage Vb prevents kickback noise [16]. The latch utilizes an n-channel cross-coupled transistor (Mn6 and Mn7) and a CMOS switch (Mn5 and Mp7).…”

Section: B Behavioral Modelmentioning

confidence: 99%

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A Frequency Model of a Continuously Driven Clocked CMOS Comparator

Okura¹,

Shibata²,

Okura³

et al. 2010

IEEE Trans. Circuits Syst. II

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A frequency model of a continuously driven clocked CMOS comparator with the effect of the input signal during regeneration is presented. The model utilizes a small-signal linear model derived from the theoretical analysis of the comparison error caused by the transition from the tracking mode to the regeneration mode. The comparison error voltage is a function of input signal frequency and is represented with the transfer function. The correctness of the model is assured by several transistor-level simulation results. The model provides a valuable insight for the design of high-speed comparators.

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Section: B Behavioral Modelmentioning

confidence: 99%

“…The time response of the comparator during the regeneration mode is given by (16) with coefficients a c1 , a c2 , and a c3 . These coefficients are respectively given by a c1 = −A preamp K 1 g min g ml sin(θ in + θ 1 ) + j cos(θ in + θ 1 ) 2(1 + jω in τ reg ) ,…”

Section: Appendixmentioning

confidence: 99%

A Frequency Model of a Continuously Driven Clocked CMOS Comparator

Okura¹,

Shibata²,

Okura³

et al. 2010

IEEE Trans. Circuits Syst. II

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“…To show that the estimates for power dissipation derived in this section are close to reality, information on 6-bit ADC's was gathered out of the open literature [59][60][61][62][63][64][65][66][67][68][69][70][71][72][73] to enable a comparison between measured data on power dissipation and power esitimates based on the above theory. Six bit ADC's were chosen for this comparison as most 6-bit design share the same architecture, that of a Flash-ADC as depicted in Fig.…”

Section: Data From Literaturementioning

confidence: 99%

“…Each paper [59][60][61][62][63][64][65][66][67][68][69][70][71][72][73] quotes an number for the Effective Number of Bits (ENOB) and Resolution Bandwidth. In our estimates we use 2 ENOB as an estimate for the Dynamic range (DR) and the Resolution BW as an estimate for the maximum signal frequency F sig .…”

Section: Data From Literaturementioning

confidence: 99%

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

Bult¹

2006

Analog Circuit Design

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A general approach for Power Dissipation estimates in Analog circuits as a function of Technology scaling is introduced. It is shown that as technology progresses to smaller dimensions and lower supply voltages, matching dominated circuits are expected to see a reduction in power dissipation whereas noise dominated circuits will see an increase. These finds are applied to ADC architectures like Flash and Pipeline ADC's and it is shown why Pipeline ADC's survive better on a high, thick-oxide supply voltage whereas Flash ADC's benefit from the technology's thinner oxides. As a result of these calculations an adaptation to the most popular Figure-of-Merit (FOM) for ADC's is proposed.

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“…In terms of power per Mds, the prototype compares favorably with most recently-published devices (e.g. [2],[3] and[5]) Over a 12 hour period of continuous operation, without re-calibration, the SNDR varied by less that O.ldB. All parts tested to date are completely functional.…”

mentioning

confidence: 69%

A 'digital' 6-bit ADC in 0.25 μm CMOS

Donovan¹,

Flynn

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirement, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0 . 2 5~ digital CMOS process occupies 1.2mm2 and dissipates llOmW from a 2.2V supply at 300Ms/s. 8-2-1 0-7803-6591~7/01/$10~00 0 2001 IEEE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE

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A 6 b 800 MSample/s CMOS A/D converter

Cited by 16 publications

References 3 publications

A Frequency Model of a Continuously Driven Clocked CMOS Comparator

A Frequency Model of a Continuously Driven Clocked CMOS Comparator

The Effect of Technology Scaling on Power Dissipation in Analog Circuits

A 'digital' 6-bit ADC in 0.25 μm CMOS

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